The invention discloses a DRM
channel modulator based on a
CORDIC algorithm. The DRM
channel modulator comprises an FPGA module used for realizing logical operation and supporting double-
clock domain operation; the
memory module is used for caching rate mismatch data between the front-stage
encoder and the rear-stage modulator; the
clock module is provided with double frequencies, the
clock module is used for serving high-speed operation and low-speed
signal processing, and the clock module realizes synchronization of two paths of clocks through an MMCM; and the high-speed AD / DA module is used for digital pre-
distortion closed-loop correction expansion.
Parallel processing of 1024 subcarriers is supported through the
assembly line
CORDIC, and the single symbol
delay is far smaller than the minimum
symbol period of the DRM. Due to the one-hot code and check bit design, the
bit error rate during
signal-to-
noise ratio is reduced by two orders of magnitude compared with that of a traditional scheme; iFFT (Inverse
Fast Fourier Transform) points can be configured, DRM30 and DRM +
modes are supported, and an existing
transmitter modulation module can be directly replaced.