Method for processing data loss caused by frequency offset in request system satellite data transmission

Abstract

The invention discloses a method for processing data loss caused by frequency offset in request-system satellite data transmission, and belongs to the technical field of satellite communication. The two-channel modulator of the dual-channel request system satellite respectively sends request frames to the data processor, and the request frames are combined and then output to the solid-state memory; the solid-state memory sends playback data of a corresponding data frame number of a single path to the data processor according to the frame number of the received request frames; the data processor averagely divides the received single-path playback data into two paths, respectively performs data processing, and generates a full identification signal; after data processing is completed, the data are output to a two-channel modulator according to the number of request frames of the path; when the full identification signal of any one of the two channels is 1, request frame combination is stopped, and at the moment, the solid-state memory pauses data playback. By detecting the capacity of the cached data in the caches in the two coding processing units in real time, the problem of data loss caused by frequency offset of a modulator clock crystal oscillator in satellite request system data transmission is reliably solved in real time.

Description

Technical Field

[0001] The present invention relates to a method for processing data loss caused by frequency deviation in on-demand satellite data transmission, belongs to the technical field of satellite communications, and particularly relates to a method for processing data loss caused by crystal oscillator frequency deviation in on-demand satellite data transmission. Background Art

[0002] In recent years, with the improvement of satellite camera resolution and the development of diversified payload types, the amount of satellite data has continued to increase. Compared with the massive growth of data, the satellite data transmission bandwidth is extremely limited. Therefore, how to improve the transmission efficiency of satellite effective data is an eternal research problem.

[0003] There are usually several ways to improve the efficiency of satellite effective data transmission: First, source coding, also known as data compression, aims to transmit the maximum amount of information with the least amount of data; the current compression methods used on board include ADPCM, JPEGLS, JPEG2000, H265, etc.; second, preprocessing technology, the purpose is to pre-process satellite data before transmission to reduce the amount of transmitted data. The current preprocessing technologies used on board include cloud detection, ship detection, and point target extraction, etc.; third, high-efficiency data transmission, the purpose is to maximize the utilization of effective bandwidth. The current on-board data transmission methods include traditional data transmission and request-based data transmission.

[0004] Traditional data transmission is a sequential process, from satellite payload data generation to data storage and processing, and then to the modulator and channel. A drawback of this transmission method is that, given limited bandwidth, the total amount of data must be less than the channel capacity to prevent data overflow and loss. Consequently, invalid data (empty frames) occupy a certain amount of channel bandwidth. Request-based data transmission is a feedback-based data transmission method. As long as the channel bandwidth allows, the modulator sends a request frame to the data processor. Upon receiving the request, the data processor, depending on the operating mode, reads data from the solid-state memory or payload and sends it to the modulator in real time. This method maximizes the transmission of valid data, while minimizing the amount of invalid data (empty frames).

[0005] In a dual-channel request-based satellite data transmission scheme, the dual-channel modulators operate independently, but the data processor and solid-state memory operate in tandem. The data processor's encoding unit synthesizes the dual-channel request frames into one request frame and sends it to the solid-state memory. Based on the request frame data content, the solid-state memory replays the corresponding amount of single-channel satellite data to the data processor's encoding unit. The data processor's encoding unit then ping-pongs the replayed data into two channels according to a specific rule. After processing each channel, the data is sent to modulators 1 and 2, respectively, based on the number of request frames. This transmission scheme works correctly when the request frames (clock crystal oscillators) of the dual-channel modulators match in frequency. However, when the clock crystal oscillators of the dual-channel modulators experience frequency shifts in opposite directions, the number of request frames changes over time. The solid-state memory then sends the corresponding amount of satellite data based on the combined request frame content. Since the satellite data lacks channel identification, the data processor's encoding unit must divide the total data into two channels. After processing each channel's data separately, the data is sent to the modulators based on the number of modulator request frames per channel. This process can result in some satellite data loss. Summary of the Invention

[0006] The technical problem solved by the present invention is to overcome the shortcomings of the existing technology and provide a method for processing data loss caused by frequency deviation in on-demand satellite data transmission. By detecting the capacity of cached data in the internal buffers of two-way encoding processing units in real time, the request frame combining signal is controlled and no longer output to the solid-state memory. This method solves the problem of data loss caused by frequency deviation of the modulator clock crystal oscillator in satellite on-demand data transmission in real time and reliably.

[0007] The technical solution of the present invention is as follows: In a first aspect, a data processor for preventing data loss caused by frequency deviation in request-based satellite data transmission comprises:

[0008] a request frame combining unit, receiving a full identification signal and a request frame sent by the two-channel modulator when the dual-channel request system satellite performs data transmission, and combining the request frames. If and only if the received full identification signal is 0, the combined request frame is output to the external solid-state memory;

[0009] A data splitting unit receives single-channel playback data of a corresponding number of data frames sent by an external solid-state memory according to the number of combined request frames, and evenly splits the single-channel playback data into two channels, and sends them to the encoding processing units corresponding to the two-channel modulators respectively;

[0010] The encoding processing unit is provided with several corresponding to the modulator channels, and is used to process the received single-channel playback data. After completing the data processing, it outputs the data to the corresponding channel modulator according to the number of request frames of the corresponding channel, and generates a full identification signal according to the amount of cached data monitored in real time during data processing and sends the full identification signal to the request frame combining unit; when the amount of cached data exceeds the preset threshold of the total cache capacity, the full identification signal is set to 1, otherwise it is set to 0.

[0011] Furthermore, the encoding processing unit includes a dual-port RAM buffer, and after completing data processing, the data is stored in the dual-port RAM buffer. The amount of data output by the buffer is determined in real time by the number of frames requested by the modulator.

[0012] In a second aspect, a method for processing data loss caused by frequency deviation in on-demand satellite data transmission using the data processor includes:

[0013] During dual-channel request-based satellite data transmission, the two-channel modulators respectively send request frames to the data processor, which then outputs the request frames to the solid-state memory after combining them. The solid-state memory sends playback data of the corresponding number of data frames on a single channel to the data processor based on the number of request frames received. The data processor evenly divides the received single-channel playback data into two channels, processes them separately, and generates a full flag signal based on the amount of cached data processed by real-time monitoring data. After completing data processing, the data is output to the corresponding channel modulator based on the number of request frames on this channel. When the amount of cached data exceeds a preset threshold of the total cache capacity, the full flag signal is set to 1, otherwise it is set to 0. When the full flag signal of either channel is 1, the request frame combining output is stopped, and the solid-state memory pauses playback data.

[0014] Furthermore, if the full flag signal becomes 1 while the combined request frame is being output, the full flag signal is delayed until the entire request frame is output to the solid-state memory.

[0015] Furthermore, the single-channel playback data is evenly divided into two channels, including: the input single-channel solid-state memory playback data, the 1st-Nth frames are divided into the first channel, the (N+1)-2Nth frames are divided into the second channel, and so on, divided into two channels of data for data processing, where N is the number of requested frames.

[0016] Furthermore, after the encoding processing unit corresponding to each channel completes data processing, it writes the data to the dual-port RAM buffer. Every time a modulator request frame is received, data of the requested frame number is read from the dual-port RAM and sent to the corresponding modulator. When the data amount in the dual-port RAM buffer exceeds 60% of the total buffer capacity, the full flag signal is set to 1, otherwise the full flag signal is set to 0.

[0017] Furthermore, if the number of valid data frames stored in the dual-port RAM buffer is less than the number of requested frames, empty frame data of a corresponding number of frames are filled.

[0018] Furthermore, the method of evenly dividing the single-channel playback data into two channels is to perform ping-pong division into two channels according to the format of the requested frame number.

[0019] In a third aspect, a computer-readable storage medium stores a computer program, wherein when the computer program is executed by a processor, the computer program implements the steps of the method for processing data loss caused by frequency deviation in request-controlled satellite data transmission.

[0020] In a fourth aspect, a device for processing data loss caused by frequency deviation in request-based satellite data transmission includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the method for processing data loss caused by frequency deviation in request-based satellite data transmission when executing the computer program.

[0021] The advantages of the present invention compared with the prior art are:

[0022] (1) The request-based satellite data transmission of the present invention is characterized by feedback-type data transmission. As long as the channel bandwidth allows, the modulator sends a request frame to the data processor. After receiving the request instruction, the data processor reads data from the solid-state memory or payload according to different working modes and sends it to the modulator in real time. Compared with traditional satellite data transmission schemes, this request-based transmission scheme can more efficiently utilize the satellite channel bandwidth and transmit valid data.

[0023] (2) The present invention provides a method for processing data loss caused by frequency deviation in demand-based satellite data transmission. This method is simple, feasible, and real-time and reliably solves the problem of data loss caused by frequency deviation of the modulator clock crystal oscillator in dual-channel demand-based satellite data transmission. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Various other advantages and benefits will become apparent to those skilled in the art upon reading the detailed description of the preferred embodiment below. The accompanying drawings are for illustration purposes only and are not to be considered as limiting the present invention. The same reference symbols are used throughout the drawings to represent the same components. In the drawings:

[0025] Figure 1 This is a principle block diagram of a method for processing data loss caused by frequency deviation in satellite data transmission.

[0026] Figure 2 This is a diagram of the request frame format.

[0027] Figure 3 This is a block diagram of the request frame combining principle.

[0028] Figure 4 This is a block diagram of the ping-pong splitting principle of playback data according to the requested frame format. DETAILED DESCRIPTION

[0029] In order to better understand the above technical solution, the technical solution of the present invention is described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the embodiments of the present invention and the specific features in the embodiments are detailed descriptions of the technical solution of the present invention, rather than limitations on the technical solution of the present invention. In the absence of conflict, the embodiments of the present invention and the technical features in the embodiments can be combined with each other.

[0030] The following is a further detailed description of a method for processing data loss caused by frequency deviation in request-based satellite data transmission provided by an embodiment of the present invention in conjunction with the accompanying drawings. Figure 1 , specific implementation methods may include:

[0031] Step A: In a dual-channel request-based satellite data transmission scheme, two-channel modulators 1 and 2 each send request frames to the data processor. The data processor combines the two request frames into one request frame signal according to the frame format and sends it to the solid-state memory. The solid-state memory then sends the corresponding number of onboard data frames to the data processor based on the number of received request frames. The data processor ping-pongs the received single-channel solid-state memory playback data into two channels based on the request frame format. After completing the data processing function, each channel outputs the requested frame number to modulators 1 and 2.

[0032] Step B: When the full flag is '0', the modulator 1 request frame signal and the modulator 2 request frame signal are combined and output to the solid-state memory; when the full flag is '1', the modulator 1 request frame signal and the modulator 2 request frame signal are not output; if the full flag becomes '1' while the combined request frame is being output, the full flag needs to be delayed until the entire frame content of the request frame is output to the solid-state memory;

[0033] Step C: The solid-state memory plays back the single-channel data, and the data processor ping-pongs the data into two channels according to the format of the requested frame number, and outputs the data to the two-channel encoding processing units; if the number of frames requested each time is N, then the 1st to Nth frames are divided into the first channel, the (N+1)th to 2Nth frames are divided into the second channel, the (2N+1)th to 3Nth frames are divided into the first channel, the (3N+1)th to 4Nth frames are divided into the second channel, and so on. The data is ping-pong-divided into two channels and output to the two encoding processing units;

[0034] Step D: After each encoding processing unit completes the encoding function, it stores the data in the dual-port RAM buffer. Each time it receives a modulator request frame, it reads the requested frame number data from the dual-port RAM and sends it to the corresponding modulator. When the accumulated time reaches a certain level, when the amount of data in the RAM buffer exceeds 60% of the total buffer capacity, a full flag signal of '1' is generated, otherwise the full flag signal is '0';

[0035] Step E: Perform an OR operation on the two full flag signals and output the full flag signal to the request frame combining unit; when any one of the full flag signals is '1', the request frame combining signal is no longer output to the solid-state memory until both full flag signals are '0', at which time the request frame combining signal is continued to be sent to the solid-state memory.

[0036] In the solution provided by the embodiment of the present invention, a method for processing data loss caused by frequency deviation in satellite data transmission is provided. The principle block diagram of the solution is shown in FIG. Figure 1 , including the following steps:

[0037] Step A:

[0038] Dual-channel modulator 1 and modulator 2 send request frames to the data processor separately; the request frame format is as follows Figure 2 As shown, the request frame data width is 16 bits, the frame length is 512 clocks, and the 5th byte of the request frame data is the request frame number N;

[0039] Step B:

[0040] (1) The data processor combines the two request frames into one, such as Figure 3 As shown in the figure, the reverse travel time of the request frame is at least (N-1) times of the forward travel time, so the two request frames have a sufficiently long reverse travel time to be combined according to the frame format; the two request frames are combined in a mechanism in which the first one comes first. If they come at the same time, the modulator 1 request frame will be output first.

[0041] (2) When the full flag signal is '0', the request frame combined signal is output to the solid-state memory. When the full flag signal is '1', the request frame combined signal is not output. If a request frame signal is being output when the full flag becomes '1', the full flag signal is delayed until the content of the current request frame is completely output. Figure 3 shown.

[0042] Step C: Each time the solid-state memory receives a request frame, it replays N frames of data to the data processor.

[0043] Step D: The data processor receives the playback data from the single-channel solid-state memory and divides the data into two channels in the format of N frames, and outputs them to the two-channel encoding processing units, such as Figure 4 As shown;

[0044] Step E:

[0045] (1) As shown in the following code, after receiving the data, the two encoding processing units perform encoding processing respectively, and then write the data into the internal buffers dual-port RAM1 and dual-port RAM2;

[0046] If (WR_cnt = B<N)=> Read out the valid data of B frame (B≥0) from RAM, fill the empty frame of NB frame, full flag FULL=0; Elsif(N≤WR_cnt<NUM×60%)=> Read N frames of valid data from RAM, full flag FULL=0;

[0047] Else (WR_cnt ≥ NUM × 60%) => read N frames of valid data from RAM, full flag FULL = 1;

[0048] End if;

[0049] Where: Wcnt: write RAM frame number; Rcnt: read RAM frame number; WR_cnt = Wcnt-Rcnt; NUM: RAM full frame number; B: RAM remaining data frame number; N: request frame number; FULL: full flag;

[0050] (2) Encoding processing unit 1 reads N frames of data from dual-port RAM 1 each time it receives a request frame from modulator 1. If the RAM does not contain N frames, it fills the data with empty frames and sends them to modulator 1. Encoding processing unit 2 reads N frames of data from dual-port RAM 2 each time it receives a request frame from modulator 2. If the RAM does not contain N frames, it fills the data with empty frames and sends them to modulator 2.

[0051] (3) When the amount of data stored in the data frame of the dual-port RAM1 is greater than 60% of the total capacity, the full flag 1 signal is '1', otherwise it is '0'; when the amount of data stored in the data frame of the dual-port RAM2 is greater than 60% of the total capacity, the full flag 2 signal is '1', otherwise it is '0';

[0052] Step F: When either the full flag 1 signal or the full flag 2 signal becomes '1', the full flag signal is '1', otherwise it is '0'.

[0053] Example 1

[0054] To further clarify the objectives, technical solutions, and advantages of the present invention, the following describes a method for addressing data loss caused by frequency offset during satellite data transmission, using examples. The present invention is further described in detail. It should be understood that the specific examples described herein are intended only to illustrate the present invention and are not intended to limit the present invention.

[0055] Step A:

[0056] (1) Dual-channel modulator 1 and modulator 2 send request frames to the data processor separately; request frames

[0057] Frame format such as Figure 2 As shown, the request frame data width is 16 bits, the frame length is 512 clocks, the frame synchronization header is "1ACFFC1D", the specific data is "441F+frame counter (23~0)+"00"", the request end address is "B1", the response end address is "C2", the request frame counter is "0000", the request frame number is "08", the reserved is "00", the CRC check bit (CRC check position is from the fifth byte to the 16th byte), and the other bytes are filled with "00".

[0058] (2) The hardware interface between the data processor and the modulator is a 2711 chip with a clock frequency of 100 MHz. The 2711 bus software interface protocol is detailed in public information and is not described in detail in this article.

[0059] Step B:

[0060] (1) The data processor combines the two request frames into one, such as Figure 3 As shown in the figure, the reverse travel time of the request frame is at least 7 times the forward travel time, so the two request frames have enough reverse travel time to be combined according to the frame format; the two request frames are combined in a mechanism that whichever comes first goes first. If they come at the same time, the modulator 1 request frame goes out first.

[0061] (2) When the full flag signal is '0', the request frame combined signal is output to the solid-state memory. When the full flag signal is '1', the request frame combined signal is not output. If a request frame signal is being output when the full flag becomes '1', the full flag signal is delayed until the content of the current request frame is completely output. Figure 3 shown.

[0062] (3) The data processor and solid-state memory use a GTX bus interface with a clock frequency of 125 MHz. The GTX bus interface protocol is detailed in public information and is not described in detail in this article.

[0063] Step C: Each time the solid-state memory receives a request frame, it replays 8 frames of data to the data processor.

[0064] Step D: The data processor receives the playback data from the solid-state memory and divides the data into two paths in a ping-pong format of 8 frames, and outputs the data to the two-path encoding processing unit, such as Figure 4 As shown;

[0065] Step E:

[0066] (1) As shown in the following code, after receiving the data, the two encoding processing units perform encoding processing respectively, and then write the data into the internal buffers dual-port RAM1 and dual-port RAM2. The total number of frames cached in the dual-port RAM is 128;

[0067] If (WR_cnt=B<8) => read B (B≥0) frames of valid data from RAM, fill 8-B frames with empty frames, full flag FULL=0; Elsif (8≤WR_cnt<80) => read 8 frames of valid data from RAM, full flag FULL=0;

[0068] Else(WR_cnt≥80)=>read 8 frames of valid data from RAM, full flag FULL=1;

[0069] End if;

[0070] Where: Wcnt: write RAM frame number; Rcnt: read RAM frame number; WR_cnt = Wcnt-Rcnt; NUM: RAM full frame number (128); B: RAM remaining data frame number; N: request frame number (8); FULL: full flag;

[0071] (2) Encoding processing unit 1 reads 8 frames of data from dual-port RAM 1 each time it receives a request frame from modulator 1. If the RAM contains less than 8 frames, it fills the data with empty frames and sends them to modulator 1. Encoding processing unit 2 reads 8 frames of data from dual-port RAM 2 each time it receives a request frame from modulator 2. If the RAM contains less than 8 frames, it fills the data with empty frames and sends them to modulator 2.

[0072] (3) When the number of data frames stored in the dual-port RAM1 is greater than 80, the full flag 1 signal is '1', otherwise it is '0'; when the number of data frames stored in the dual-port RAM2 is greater than 80, the full flag 2 signal is '1', otherwise it is '0';

[0073] Step F: When either the full flag 1 signal or the full flag 2 signal becomes '1', the full flag signal is '1', otherwise it is '0'.

[0074] The present invention provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer instructions, which, when executed on a computer, cause the computer to execute Figure 1 The method described.

[0075] Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, systems, or computer program products. Thus, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware. Furthermore, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage and optical storage, etc.) containing computer-usable program code.

[0076] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowcharts and / or block diagrams, as well as combinations of processes and / or blocks in the flowcharts and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowcharts and / or block diagrams. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0077] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0078] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0079] Obviously, those skilled in the art may make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if such changes and modifications fall within the scope of the claims and their equivalents, the present invention is intended to include such changes and modifications.

[0080] The contents not described in detail in the specification of the present invention belong to the common knowledge of those skilled in the art.

Claims

1. A data processor for preventing data loss caused by frequency deviation in on-demand satellite data transmission, characterized in that: include: a request frame combining unit, receiving a full identification signal and a request frame sent by the two-channel modulator when the dual-channel request system satellite performs data transmission, and combining the request frames. If and only if the received full identification signal is 0, the combined request frame is output to the external solid-state memory; A data splitting unit receives single-channel playback data of a corresponding number of data frames sent by an external solid-state memory according to the number of combined request frames, and evenly splits the single-channel playback data into two channels, and sends them to the encoding processing units corresponding to the two-channel modulators respectively; The encoding processing unit is provided with several corresponding to the modulator channels, and is used to process the received single-channel playback data. After completing the data processing, it outputs the data to the corresponding channel modulator according to the number of request frames of the corresponding channel, and generates a full identification signal according to the amount of cached data monitored in real time during data processing and sends the full identification signal to the request frame combining unit; when the amount of cached data exceeds the preset threshold of the total cache capacity, the full identification signal is set to 1, otherwise it is set to 0.

2. The data processor according to claim 1, wherein: The encoding processing unit includes a dual-port RAM buffer. After completing data processing, the data is stored in the dual-port RAM buffer. The amount of data output by the buffer is determined in real time by the number of frames requested by the modulator.

3. A method for processing data loss caused by frequency deviation in on-demand satellite data transmission implemented by the data processor according to claim 1 or 2, characterized in that: include: When dual-channel request-based satellite data transmission is used, the two-channel modulators send request frames to the data processor respectively. The data processor combines the request frames and outputs them to the solid-state memory. The solid-state memory sends playback data of a corresponding number of data frames in a single channel to a data processor based on the number of frames of the received request frames; the data processor divides the received single-channel playback data into two channels, processes the data separately, and generates a full identification signal based on the amount of cached data processed by real-time monitoring data; after completing the data processing, it outputs the data to the corresponding channel modulator based on the number of request frames in this channel; when the amount of cached data exceeds the preset threshold of the total cache capacity, the full identification signal is set to 1, otherwise it is set to 0; when the full identification signal of either of the two channels is 1, the request frame combination output is stopped, and at this time the solid-state memory suspends the playback data.

4. The method for processing data loss caused by frequency deviation in on-demand satellite data transmission according to claim 3, characterized in that: If the full flag signal changes to 1 while the combined request frame is being output, the full flag signal is delayed until the entire request frame is output to the solid-state memory.

5. The method for processing data loss caused by frequency deviation in on-demand satellite data transmission according to claim 3, characterized in that: The single-channel playback data is evenly divided into two channels, including: the input single-channel solid-state memory playback data, the 1-N frames are divided into the first channel, the (N+1)-2N frames are divided into the second channel, and so on, and the data is divided into two channels for data processing, where N is the number of requested frames.

6. The method for processing data loss caused by frequency deviation in on-demand satellite data transmission according to claim 3, characterized in that: After the encoding processing unit corresponding to each channel completes data processing, it writes the data to the dual-port RAM buffer. Every time a modulator request frame is received, the data of the requested frame number is read from the dual-port RAM and sent to the corresponding modulator. When the amount of data in the dual-port RAM buffer exceeds 60% of the total buffer capacity, the full flag signal is set to 1, otherwise the full flag signal is set to 0.

7. The method for processing data loss caused by frequency deviation in on-demand satellite data transmission according to claim 6, characterized in that: If the number of valid data frames stored in the dual-port RAM buffer is less than the number of requested frames, empty frame data of the corresponding number of frames will be filled.

8. The method for processing data loss caused by frequency deviation in on-demand satellite data transmission according to claim 3, characterized in that: The method for evenly dividing the single-channel playback data into two channels is to perform ping-pong division into two channels according to the format of the requested frame number.

9. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 3 to 8 are implemented.

10. A device for processing data loss caused by frequency deviation in request-controlled satellite data transmission, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the steps of the method according to any one of claims 3 to 8 are implemented.

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