Time slot synchronization method for resisting sampling clock frequency deviation in WCDMA (Wideband Code Division Multiple Access) system
A technology of frequency deviation and time slot synchronization, which is applied in the field of communication and can solve problems such as implementation complexity
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[0050] Such as figure 2 As shown, the schematic block diagram of the working principle structure in the implementation process of this embodiment, the structure of this embodiment includes a frequency deviation estimation and compensation module 201, an equal interval down-sampling module 202, a main synchronization code correlator group 203, and a correlation value normalization module 204 , a correlation value comparison and selection module 205 , a time slot boundary point search module 206 , and a time slot boundary point serial number calculation module 207 .
[0051] Such as image 3 As shown, this embodiment includes the following steps:
[0052] Step 301, according to the frequency deviation estimation method described in the first step in the summary of the invention, the frequency deviation estimation is performed on the input 8 times oversampled digital baseband signal, and the frequency deviation estimation value Δf is obtained e ; According to the estimated val...
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