Low-power-consumption readout circuit based on folding comparator and control method

A technology for reading circuits and comparators, applied in instruments, static memory, digital memory information, etc., to achieve the effects of small hardware consumption, increased output swing and gain, and improved reliability
CN104795093AActive Publication Date: 2015-07-22铠强科技(平潭)有限公司
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
铠强科技(平潭)有限公司
Publication Date
2015-07-22

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Abstract

The invention relates to a low-power-consumption readout circuit based on a folding comparator and a control method. The readout circuit comprises a folding cascade comparator, and a control circuit, a parallel magnetic tunnel junction, a control logic circuit and a phase inverter which are connected with the folding cascade comparator, wherein the control circuit is connected with the parallel magnetic tunnel junction; the phase inverter is further connected with the a first D trigger and a second D trigger; the readout circuit further comprises a time output module; the first clock signal output terminal and the second clock signal output terminal of the time output module are respectively connected with the clock control input terminals of the first D trigger and the second D trigger. The readout circuit can effectively improve the readout speed, reduces the power consumption of operating circuit during stand-by time by adding the control circuit, increases the output range and gain, and improves the reliability of the whole readout circuit when the readout circuit is butted with a digital system.
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Description

technical field

[0001] The invention relates to a low power consumption reading circuit and a control method based on a folding comparator. Background technique

[0002] Traditional Random Access Memory (RAM) such as Dynamic Random Access Memory (DRAM) is relatively inexpensive, but has slower access speeds, poor durability and data can only be stored for a short period of time. Since the data must be refreshed once in a while, this in turn leads to higher power consumption. Static random access memory (SRAM) has the advantages of fast access speed, low power consumption, and non-volatility, but it is expensive and has low integration.

[0003] In recent years, the emerging spin transfer torque random access memory (STT-RAM) is expected to become the first choice for future caches due to its high density, low leakage current, non-volatility, ultra-long durability, and fast read and write. product.

[0004] This patent is based on a novel tree-type reading circuit scheme, ...

Claims

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