Data processing method and device

Abstract

The invention relates to a data processing method and a device. Program codes running on a serially connected multiprocessor nuclear structure are partitioned according to specific rules, so that the serially connected multiprocessor nuclear structure forms a serial multi-emitting and production line layered structure, and the time required for running corresponding code fragments obtained by partitioning on each nucleus is equal as much as possible, thereby realizing the load balance of internuclear workload.

Description

technical field [0001] The present invention relates to the field of integrated circuit design. Background technique [0002] According to Moore's law, the characteristic size of transistors is gradually shrinking along the route of 65nm, 45nm, 32nm..., and the number of transistors integrated on a single chip has exceeded one billion. However, since the introduction of synthesis and layout and routing tools in the 1980s, which liberated the productivity of back-end design, EDA tools have not made a qualitative breakthrough for more than 20 years, making front-end design, especially verification, more and more difficult to cope with the increasing single chip scale. Therefore, design companies turn their attention to multi-core, that is, integrate multiple relatively simple cores in one chip, which can reduce the difficulty of design and verification while improving chip functions. [0003] Traditional multi-core processors integrate multiple processor cores that execute p...

AI Technical Summary

Problems solved by technology

Although multiple processor cores can perform parallel operations, for a single program thread, its serial execution structure makes it impossible to achieve true pipeline operation in the traditional multi-core processor structure.

In addition, there are still a large number of programs that must be executed serially in the current software, which cannot be well divided

Therefore, when the number of processor cores reaches a certain number, the performance can no longer be improved with the increase of the number of cores.

In addition, with the continuous improvement of the semiconductor manufacturing process, the internal operating frequency of the multi-core processor has been much higher than the operating frequency of its external memory. Simultaneous memory access by multiple processor cores has also become a major bottleneck restricting system performance. Parallel multi-core structure running serial programs cannot achieve the expected performance improvement effect

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