34results about How to "Solve the speed bottleneck" patented technology

The invention relates to a distributed audio and video file processing system which comprises an input processing unit, multiple video data processing units, multiple audio data processing units, an output processing unit and a dispatching unit. The input processing unit is used for receiving and processing source video files to acquire video data and audio data, and the video data and the audio data are respectively subjected to segmentation process; the video data processing units are respectively used for processing the video data subjected to the segmentation process; the audio data processing units are respectively used for processing the audio data subjected to the segmentation process; the output processing unit is used for processing and outputting the processed video data and audio data; the dispatching unit is used for coordinating operation of the input processing unit, the video data processing units, the audio data processing units and the output processing unit. Meanwhile, the invention further provides a distributed audio and video file processing method and a distributed audio and video file processing device.

The invention relates to a system for realizing SM4 algorithm at a super-speed. The system comprises a control module, a cipher-expanding/ciphering/deciphering module, a ciphering/deciphering module, a ciphering/deciphering module, a data channel subdivider, a cipher-expanding/ciphering and deciphering selector, a round cipher/result channel subdivider and a result selector. The system provided by the invention solves the problem that the speed is low in the existing hardware system as 32 round keys are computed to cipher, and during single task operation, the treatment speed can reach nearly two folds of the existing hardware system. Based on the thought of module reusability, three tasks are synchronously ciphered and deciphered, and the problem that a deciphering module is idle during frequent ciphering tasks in conventional design is solved, so that the utilization ratio and operating speed of the system are effectively improved; during multi-task operation without changing the keys, the processing speed reaches three times that of the single-task operation, the fastest six times that of the existing hardware system.

The invention provides a distributed audio and video file processing system which comprises an input processing unit, multiple video data processing units, multiple audio data processing units, an output processing unit and a dispatching unit. The input processing unit is used for receiving and processing source video files to acquire audio and video data, the audio and video data are respectively segmented into audio and video data fragments which are dispatched to corresponding audio and video data processing units for processing according to a certain dispatching rule; the video data processing units are respectively used for processing the segmented video data fragments; the audio data processing units are respectively used for processing the segmented audio data fragments; the output processing unit is used for processing and outputting the processed audio and video data fragments; the dispatching unit is used for coordinating operation of the input processing unit, the audio and video data processing units and the output processing unit. The invention further provides a distributed audio and video file processing method and a distributed audio and video file processing device.

The invention discloses a design method of an LDPC (Low-Density Parity-Check Code) decoder compatible with a DVB-S2X standard, which mainly solves the problem of long iteration time of a decoder in an existing system. The design method of the LDPC decoder compatible with the DVB-S2X standard comprises the implementing steps of 1, designing a data buffer, converting input single-path data into 360-path parallel data after the input single-path data are subjected to sequence adjustment, buffering the 360-path parallel data and carrying out decoding initiation for the data; 2, designing a first barrel-shaped shifting module, shifting the 360-path data after variable node updating and carrying out check node updating; 3, designing a second barrel-shaped shifting module, and shifting the 360-path data after the check node updating is finished and then carrying out variable node updating; 4, after the number of decoding iterations reaches to the set maximum number of iterations, calculating hard decision information for the 360-path data; and 5, after the hard decision information is subjected to the decoding decision, outputting the hard decision information in sequence so as to finish the decoding. According to the design method of the LDPC decoder compatible with the DVB-S2X standard, the iteration time of the LDPC decoder is reduced, and the throughput of the decoder is increased by one time.

The invention discloses a network data loading method. The method is applied to a Node server and comprises the following steps of receiving an access request sent by a front end server, and judging whether the access request is a page access request or not; obtaining a page identity in the page access request if the access request is the page access request; judging whether a preset static page identity set comprises the page identity or not; processing the page access request if the preset static page identity set comprises the page identity, and sending page data to the front end server; sending the page access request to a rear end server if the preset static page identity set does not comprise the page identity; and receiving feedback information sent by the rear end server based on the page access request, and sending the feedback information to the front end server, thereby enabling the front end server to carry out rendering to generate a corresponding network page. The invention also discloses a network data loading device and equipment and a computer memory medium. According to the method, the device, the equipment and the computer memory medium, data processing efficiency is improved.

The embodiment of the invention discloses a data input method based on OBD equipment, relates to the technical field of high-concurrency data processing, and can ensure timeliness of the real-time monitoring process of the OBD equipment and ease data congestion. The data input method based on the OBD equipment comprises the steps that data transmitted to a server by the OBD equipment according to a UDP/IP protocol are received by the server; the received data are taken out of a memory queue through the multi-service processing thread, the header of the received data is parsed, uplink entities are correspondingly generated according to the key words of the header, and the uplink entities are added to an uplink entity queue; downlink entities are generated according to the processing result of the uplink entity queue and pressed in a downlink entity queue, downlink messages are generated according to the downlink entities, and the downlink messages are added to a downlink information queue; and downlink information is issued to the OBD equipment according to the downlink information queue. The data input method based on the OBD equipment is suitable for data interaction with the OBD equipment.

The invention discloses a data transmission method and a data transmission device for providing a serial and parallel combination transmission mode between a transmitting end and a receiving end. A plurality of control lines and a plurality of data lines are connected between the transmitting end and the receiving end, and the data lines can be increased based on a primary serial structure. The method comprises the following steps: packing data to be transmitted into a plurality of data packets according to the data lines and the data transmission mode at the transmitting end and distributing the data packets onto the plurality of data lines respectively; transmitting the plurality of data packets through the plurality of data lines respectively, wherein the data lines transmit the data packets in a serial mode; and receiving a plurality of data blocks at the receiving end respectively and recovering the data blocks into original data.

The invention provides an FPGA based IPv6 data packet high-speed processing device and an operational method thereof, and belongs to the technical field of transceiving processing of the data packet. The device comprises a microprocessor interface module, an IPv6 data packet encapsulating transmission module, an IPv6 data packet decapsulation analysis module, an Ethernet MAC controller module, an SRAM controller module and a user interactive module, wherein the microprocessor interface module is connected with an external microprocessor, the IPv6 data packet encapsulating transmission module, the IPv6 data packet decapsulation analysis module, the SRAM controller module and the user interactive module respectively; and the IPv6 data packet encapsulating transmission module and the IPv6 data packet decapsulation analysis module are connected with the Ethernet MAC controller module respectively. The device has the advantages that: the IPv6 is fully supported, the speed of processing the network data is greatly improved, the modularization design is adopted, and various microprocessors or bus interfaces are adapted only by modifying the microprocessor interface module, so that the device is high in expansibility, versatility and flexibility.

Provided is a high speed two-mode16/17 prescaler circuit belonging to high speed frequency synthesizer and high frequency transceiver technology field. The prescaler circuit comprises three positive edge triggers, a two input or a door, a two input or a non-door, a three input and a non-door and two negative edge triggers. The synchronization frequency division unit composed by the three positive edge trigger, the two input or door and the two input and the non-door adopts rising edge trigger except 4/5. The asynchronization frequency division unit composed by the two negative edge triggers adopts fall edge trigger except 4. The feedback control unit adopts the three input and the non-door. The prescaler circuit prevents the influence of the feedback path to the speed of the prescale in 17 frequency division in the existing technology and reduces the delay of the feedback path thus preventing the influence of the feedback state to the synchronization 4/5 frequency division speed, increasing the speed of the prescaler, solving the bottleneck problem of speed of the frequency synthesizer and realizing well the 16/17 high frequency division of the prescaler.

The invention relates to the field of bottle blowing machines, in particular to a servo motor mold opening and closing mechanism for a rotary bottle blowing machine. A hanging-lug-type mold carrier is adopted. The servo motor mold opening and closing mechanism comprises a connecting assembly connected to the hanging-lug-type mold carrier, and the connecting assembly is connected with a servo motor through a lead-screw and bushing transmitting mechanism. According to the servo motor mold opening and closing mechanism for the rotary bottle blowing machine, as the hanging-lug-type mold carrier, the connecting assembly, the lead-screw and bushing transmitting mechanism and the servo motor are arranged, track-free mold opening and closing control is achieved, and the multiple defects of a rotating speed bottleneck, serious abrasion, poor mold assembling-disassembling precision and poor mechanical stability of a track mold opening and closing mechanism in the prior art are overcome.

The invention provides a low-frequency string-wave signal phase difference measurement method and belongs to the field of phase different measurement with an aim to solve problems that existing phase difference measurement is complex in circuit structure and low in measurement accuracy. The low-frequency string-wave signal phase difference measurement method includes: subjecting two same-frequency string-wave signals acquired synchronously to no-signifying processing to acquire a first signal and a second signal which are to be process in an FPGA (field programmable gate array); sequentially determining self-correlation measurement value of the first signal, self-correlation measurement value of the second signal and cross-correlation measurement value of the first and second signals; according to noise and signal correlation features, acquiring self-correlation theoretical value of the first signal, self-correlation theoretical value of the second signal and cross-correlation theoretical value of the first and second signals; according to amplitude of the two same-frequency string-wave signals, the self-correlation theoretical value, the self-correlation theoretical value, the cross-correlation theoretical value of the first and second signals and an arbitrary-angle function relation formula, determining the phase difference of the same-frequency string-wave signals.

The embodiment of the invention discloses a fully-automatic bag fetching and opening machine. The fully-automatic bag fetching and opening machine comprises a lower opening mechanism, an upper openingmechanism and a bag fetching arm. A bag storage unit is fixedly arranged behind the lower opening mechanism and can move back and forth along with the lower opening mechanism. The upper opening mechanism is arranged on a longitudinal movement mechanism. The lower opening mechanism and the upper opening mechanism are each provided with a gluing mechanism. Each gluing mechanism comprises gluing wheels. Each gluing wheel is provided with adhesive tape. The adhesive face of each piece of adhesive tape faces the side away from the corresponding gluing wheel. The bag fetching arm is connected witha swing shaft through a hinge-joint seat and can be driven by the swing shaft to swing forwards and backwards. According to the fully-automatic bag fetching and opening machine, by means of the loweropening mechanism, the upper opening mechanism and the bag fetching arm, packaging bags can be fetched, opened and connected into a discharging mechanism in a sleeved manner fully automatically; the discharging speed is greatly increased while manpower is saved; and the main speed bottleneck problem found in the material packaging process is solved.

The invention discloses a laser gyroscope frequency stabilization control system and method based on a DSP and an FPGA. The system comprises piezoelectric ceramic and an annular resonant cavity, and further comprises a light intensity detection device, an SBS detection device, a light intensity filter circuit, an A/D converter, a D/A converter, a high-voltage amplification circuit and a microprocessor, and the microprocessor comprises a DSP main processor and an FPGA coprocessor; the light intensity detection device is connected with the light intensity filter circuit, the light intensity filter circuit and the SBS detection device are electrically connected with the A/D converter, the A/D converter is connected with the FPGA coprocessor, the FPGA coprocessor is communicated with the DSP main processor, and the DSP main processor is connected with the upper computer; and the FPGA coprocessor is electrically connected with an input port of the D/A converter. The laser gyroscope frequency stabilization control system and method based on the DSP and the FPGA have the differential push-pull frequency stabilization function, and the measurement precision of the laser gyroscope is improved.

The invention discloses an implementation method for guaranteeing the real-time performance of semi-physical simulation by a three-layer structure, which aims at the real-time performance requirement of a semi-physical simulation system, starts from the top design and software and hardware, and is implemented by adopting a mode of reasonable division and mutual cooperation of hardware and software functions. A multi-core CPU is divided into two parts, wherein one part is that under RTX, threads where codes with high requirements for real-time performance are located independently occupy one CPU physical core respectively; the other part of the CPU is reserved in Windows to execute the codes that are time-consuming but not high in real-time requirement; the codes are divided into three layers on software, wherein the first layer is simulation and communication codes with high requirements on real-time performance; the second layer is a low-speed IO operation code; and the third layer is user interface codes. The division mode fully ensures that the real-time requirement of the semi-physical simulation is met, and ensures that threads where codes with high real-time requirement in the semi-physical simulation software are located can occupy CPU resources at any time and scheduling waiting does not occur. The third layer in the three-layer structure also provides a wide space for the design of the user interface, and the user interface of the third layer can use various UI design and programming languages based on the isolation effect of the second layer.