System for realizing SM4 algorithm at super-speed as well as operating method of system

An ultra-high-speed, algorithmic technology, applied in the direction of encryption devices with shift registers/memory, etc., can solve the problems of reducing the operation processing speed, reducing the data processing speed, and failing to meet the requirements.

Active Publication Date: 2015-04-29
BINZHOU POLYTECHNIC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This patent has the following defects: a decryption operation needs to go through 96 rounds of iterations, which seriously reduces the data processing speed, and is not suitable for some occasions that require high speed
[0007] The above two patents are dedicated to reducing the area and redundancy of the system and combining the key expansion module with the encryption/decryption module. However, since the key expansion and data encryption/decryption cannot be performed simultaneously, an encryption operation must go through 32 Round key expansion and 32 rounds of encryption have a total of 64 rounds of iteration time, which seriously reduces the data processing speed and is not suitable for some occasions that require high speed
[0008] In the traditional design, the key expansion module, the encryption module and the decryption module are separated, and the method of starting the encryption module after waiting for 32 rounds of key calculation i

Method used

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  • System for realizing SM4 algorithm at super-speed as well as operating method of system
  • System for realizing SM4 algorithm at super-speed as well as operating method of system
  • System for realizing SM4 algorithm at super-speed as well as operating method of system

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0155] An ultra-high-speed system for implementing the SM4 algorithm, comprising: a control module 1, a cryptographic expansion / encryption / decryption module 19, an encryption / decryption module 20, a decryption / encryption module 21, a data splitter 17, and a cryptographic expansion / encryption / decryption selector 18. Wheel secret / result splitter 22, result selector 23, the control module 1 includes a microprocessor interface 12, a startup module 2, a data path module 3, a data cache area 5, a comparator 4, and an exclusive OR operation module 15 and new / old round secret selector 16, described data cache area 5 comprises old key storage area 6, new key storage area 7, system parameter storage area 8, intrinsic parameter storage area 9, original data storage area 10, Old round secret storage area 11, new round secret storage area 13 and result data storage area 14;

[0156] The microprocessor interface 12 is connected to the microprocessor; the three groups of iterations input of ...

Embodiment 2

[0159] According to the system described in Embodiment 1, the difference is that the dense expansion / encryption / decryption module 19 includes a bidirectional shift register group, a D flip-flop group with retention, a state machine module 31, an F / F' transformation module 43, Band enable optional D flip-flop group, the bidirectional shift register group is a four-input 32-bit bidirectional shift register U0_332, and the four-input 32-bit bidirectional shift register U0_332 includes four 32-bit registers, namely U0 — U3, the D flip-flop group with hold is a 32-bit D flip-flop U430 with hold function, and the D flip-flop group with enable option is a 32-bit D flip-flop with an optional input for output enable Device Yd44;

[0160] The data input module of described dense expansion / encryption / decryption module 19 comprises described four input 32-bit bidirectional shift register U0_332 and the 32-bit D flip-flop U430 of described band holding function, and described dense expansi...

Embodiment 3

[0163] According to the system described in embodiment 1 or embodiment 2, the difference is that the instruction output, key output, and data output of the microprocessor interface 12 are respectively connected to the instruction input and the new key storage area 7 of the startup module 2 And the input of comparator 4, the input of original data storage area 10; The input of described comparator 4 connects the key output of described microprocessor interface 12 and the output of old round secret storage area 11; The output of described comparator 4 The output is connected to the comparison signal input of the startup module 2; the enable signal output en1 and en0 of the startup module 2 are respectively connected to the enable input and new password of the new round secret storage area 13 assigned to the old round secret storage area 11. The key storage area 7 is assigned to the enable input of the old key storage area 6; the three module data number outputs of the startup mod...

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PUM

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Abstract

The invention relates to a system for realizing SM4 algorithm at a super-speed. The system comprises a control module, a cipher-expanding/ciphering/deciphering module, a ciphering/deciphering module, a ciphering/deciphering module, a data channel subdivider, a cipher-expanding/ciphering and deciphering selector, a round cipher/result channel subdivider and a result selector. The system provided by the invention solves the problem that the speed is low in the existing hardware system as 32 round keys are computed to cipher, and during single task operation, the treatment speed can reach nearly two folds of the existing hardware system. Based on the thought of module reusability, three tasks are synchronously ciphered and deciphered, and the problem that a deciphering module is idle during frequent ciphering tasks in conventional design is solved, so that the utilization ratio and operating speed of the system are effectively improved; during multi-task operation without changing the keys, the processing speed reaches three times that of the single-task operation, the fastest six times that of the existing hardware system.

Description

technical field [0001] The invention relates to an ultra-high-speed implementation of SM4 algorithm system and its operation method, belonging to the technical field of information encryption. Background technique [0002] In March 2012, the State Encryption Security Administration officially established the SM4 block cipher algorithm as an industry standard. At present, the SM4 standard has been commercially promoted on a certain scale in some fields in my country. In the next ten years, wireless local area network, finance, national defense, e-commerce, video encryption and other fields will need nearly 100 million SM4 algorithm encryption and decryption systems. Therefore, the development of high-performance SM4 algorithm encryption and decryption systems has become a hot spot in the industry. [0003] The SM4 algorithm is a block cipher algorithm with a data length of 128 bits and a key length of 128 bits. The key undergoes 32 nonlinear iterative operations to generate ...

Claims

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Application Information

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IPC IPC(8): H04L9/06
Inventor 吕茜曹艳艳
Owner BINZHOU POLYTECHNIC
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