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Method and device for debugging parallel programs based on application logical orders

A technology for application logic and program debugging, applied in the computer field, can solve problems such as prolonged program execution time, high debugging overhead, and difficulty in parallel tasks, and achieves a solution that is conducive to error location, reduction of logic sequence information, and saving storage and analysis overhead. Effect

Active Publication Date: 2013-02-13
JIANGNAN INST OF COMPUTING TECH
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Problems solved by technology

But this method is not necessarily suitable for parallel programs. The main defects are: 1. It is difficult to reversely execute logically related parallel tasks; If the process takes a long time, the debugging overhead will be quite large; 3. It still needs to occupy parallel computing resources for a long time and perform manual debugging

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  • Method and device for debugging parallel programs based on application logical orders
  • Method and device for debugging parallel programs based on application logical orders
  • Method and device for debugging parallel programs based on application logical orders

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Embodiment Construction

[0030] Due to the complex semantics of parallel programs, it includes not only the logic of the task itself, but also the interaction logic between tasks executed in parallel, and even between multiple parallel programs. The two logics are intertwined, resulting in a program that may fail when one logic goes wrong. Continue to execute for a while, report an error on a seemingly irrelevant logic, and even run to the end, but the calculation result is incorrect. So verifying the correctness of parallel programs must combine the two logical behaviors of the program.

[0031] The technical idea of ​​the present invention is based on an abstract model describing the two logics of the parallel program, establishes the association between the physical quantity of the application system and the variable of the parallel program, combines the application semantics to verify the correct value of the program variable in an organized manner, and then verifies the semantics of the parallel p...

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Abstract

The invention discloses a method and a device for debugging parallel programs based on application logical orders. The method for debugging parallel programs includes defining data chains and abstractly describing semantic logics of complex parallel programs, wherein the data chains comprise application logical orders, logic fragment assembles and a correctness verification algorithm, and the application logical orders are iteration step orders or data flow orders; data of program variables during parallel program operation are tracked according to definitions of the data chains, and the data of the program variables are verified by the correctness verification algorithm and verification results are recorded; and the recorded verification results are reset when the parallel program stops operation or is exited abnormally. The method and the device are based on a reset debugging plan of parallel application system semantic logics, error locating of parallel programs is facilitated, and storage and analysis expenditures are saved.

Description

technical field [0001] The invention relates to the field of computer technology, in particular to a parallel program debugging method and device based on an application logic sequence. Background technique [0002] At present, parallel computing has become an important support for many scientific research and production fields, and has become a symbol of the development level of productivity. However, the carrier that parallel computing relies on, that is, parallel programs, lacks effective software debugging tools, which seriously affects the utilization rate of high-performance computers and the level of parallel computing. improvement. Parallel programs currently mainly adopt the debugging method of serial programs, that is, breakpoint debugging, which relies on manual operation and is inefficient. It requires a considerable understanding of the implementation principles and details of the parallel support environment, because this debugging method was originally propose...

Claims

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Application Information

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IPC IPC(8): G06F11/36
Inventor 王敬宇陈华蓉冯赟龙王雯霞
Owner JIANGNAN INST OF COMPUTING TECH
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