64 results about "Decoding latency" patented technology

Certain aspects of the present disclosure relate to techniques and apparatus for improving decoding latency and performance of Polar codes. An exemplary method generally includes generating a codeword by encoding information bits, using a multi-dimensional interpretation of a polar code of length N, determining, based on one or more criteria, a plurality of locations within the codeword to insert error correction codes generating the error correction codes based on corresponding portions of the information bits, inserting the error correction codes at the determined plurality of locations, and transmitting the codeword. Other aspects, embodiments, and features are also claimed and described.

The present invention relates to transmission and reception of data over a plastic optical fiber. In particular, the present invention provides for transmission and reception over the plastic optical fiber a particularly suitable frame structure. The frame structure includes a synchronization sequence and portions of user data alternating with alternating reference signal portions and control data portions. The length of the user data portions may be equal, the length of the synchronization sequence and the control data and reference signal portions may also be equal. The distances between the synchronization sequence and the reference signal portions and the control data portions are advantageously equal. The alternating of data and additional information avoids data decoding latency while maintaining the rate necessary for the additional information.

An apparatus for transmitting a FEC frame is provided. In order to correct an error caused by a transmission medium using FEC in a Reed-Solomon code type, FEC encoding / decoding of a frame is performed. A total transmission delay time is not influenced when FEC is bypassed, a delay caused by a shortened codeword is minimized, and a FEC encoding / decoding delays for frames having different lengths are equalized.

A processing load at the time of playing back sound data having a loop part is reduced.A sound data encoding apparatus comprises a block dividing means that divides the sound data into blocks according to predetermined rules, and an encoding means that encodes the blocks in groups of a plurality of consecutive blocks. The block dividing means divides the sound data such that, when encoded blocks encoded by the encoding means are decoded to output decoded blocks, then the loop end position in a block that includes the loop end position in the decoded blocks is nearer to an end of the block than a predetermined position. In detail, input delay dummy data are added ahead of the sound data before dividing the sound data. At the time of outputting the encoded data, loop information is outputted also. The loop information includes the number of samples of the added input delay dummy data, the number of samples corresponding to the encoding delay, the number of samples corresponding to the decoding delay, the start and end positions of the sound data, and the loop start and end positions.

Methods, apparatus and systems are disclosed for block encoding / decoding information wireless networks having narrow decoding latency restrictions. A method includes identifying a length of information to be sent in a block code and encoding the information to be sent in the block code into one or more codewords, where the number of codewords and the amount of information encoded within each codeword is adjusted based on the identified length and to achieve a similar codeword error probability for each codeword considering available decoding time for decoding a last codeword is less than available decoding time for decoding a first codeword. In certain implementations low density parity check (LDPC) encoding may be used in combination with OFDM to provide reliable communications in a high throughput WLAN.

Certain aspects of the present disclosure relate to techniques and apparatus for improving decoding latency and performance of Polar codes. An exemplary method generally includes generating a codeword by encoding information bits using a first code of length K to obtain bits for transmission via K channels, wherein the first code comprises a polar code, further encoding the bits in each of the K channels using a second code of length M, and transmitting the codeword.

To control a decoding latency, larger blocks are nonequally segmented into smaller ones. The decoding process starts directly after reception of the first small block. The latency is defined by the latency of the last small block decoding. Changing the number of iterations during the turbo-code decoding also permits control of the decoding latency.

Self-configuring error control coding in a memory device provides flexibility in terms of decoding latency, mis-correct probability, and bit-error rate performance, and avoids labor-intensive trial-and-error configuration of decoding algorithm tuning parameters, such as bit flip algorithm thresholds and syndrome-weight maps. A self-configuring decoder for error control coding allows dynamic trading of error floor performance for error rate performance and vice versa based on the performance characteristics of the decoding process.

A method and device for improving rate controlling in video coding of sequences including a series of Inter frames separated by Intra frames, when a decoding delay is considered, comprise for each Inter frame of the series: computing a target frame size, computing a maximum buffer level related to a position of each Inter frame relative to a previous Intra frame and an upcoming Intra frame, and optimizing a transmission buffer level in response to the computed target frame size and the computed maximum buffer level.