33 results about "Decoding latency" patented technology

The application provides a polar code soft input soft output decoding method, a decoding device and a communication device; the decoding method comprises the following steps: (S1) performing fast serial cancellation list decoding under dynamic frozen bit constraint for all special nodes constituting a polar code; the types of the special nodes comprise rate zero, rate one, repetition and single parity check; (S2) calculating the approximation of the sum of the posterior probabilities of the legal code words not accessed under each special node after decoding; (S3) using the approximation of the code book probability obtained in the step (S2) to calculate the bit level soft information of the output polar code. The low-latency polar code soft input soft output decoding method provided by the application improves the parallelism by realizing fast soft output decoding based on the Rate0, Rate1, REP and SPC nodes, and significantly reduces the decoding latency without losing the soft output precision compared with the SO-SCL decoding algorithm.

Systems and methods for error detection in quantum computing systems are provided. In one example, the method includes obtaining a multi-dimensional quantum error detection map. The multi-dimensional quantum error detection map represents one or more quantum error detection measurements over a period of time. The method includes determining a partitioning scheme and a fusion scheme for the multi-dimensional quantum error detection map based at least in part on the decoding delay and the fusion delay. The method includes partitioning the multi-dimensional quantum error detection map into a plurality of blocks based at least in part on the partitioning scheme. The method includes decoding each of the plurality of blocks. The method includes fusing the plurality of blocks into a decoded detection map based at least in part on the fusion scheme. The method includes operating a quantum computing system based at least in part on the decoded detection map.

A shared decoder pool is susceptible to head-of-line blocking when the decoding of a given data block delays the decoding of other data blocks pipelined in the decoder. While the problem can be avoided by not using a pipeline operation, the benefits of pipelining would be lost. In one embodiment provided herein, the syndrome of an error pattern is calculated in parallel with data being written in an input buffer for the decoder. Parallelizing the syndrome calculation and the filling of the decoder's input buffer can avoid the head-of-line blocking problem noted above while still achieving the benefits of pipelining. In another embodiment, a similar technique is used in a bit error rate estimation scan (BES) operation. Other embodiments are provided.

Communication systems that utilize receivers for decoding short block length messages are disclosed. In many embodiments, the receiver includes an antenna for receiving encoded data, via RF signals, a demodulator for obtaining symbols from the RF signal, a demapper for generating symbol metrics, and a parallel list decoder. In several embodiments, the parallel list decoder processes multiple trellis stages simultaneously, enabling efficient decoding of the symbol metrics to obtain received, bits. In certain embodiments, the parallel list decoder divides the decoding trellis into segments, processes these segments independently, and combines them pairwise to form new segments. This parallel processing approach can allow for reduced decoding latency and improved efficiency in handling short block length messages. making it particularly suitable for applications requiring rapid data exchange and low-latency communication.

This application provides a method and communication apparatus for channel coding or decoding. It can generate new insertion rows based on adjacent rows of the basis matrix in the NR, or it can generate new insertion rows based on a specific row in the basis matrix of the NR, thereby expanding the basis matrix in the NR. The expanded basis matrix can be flexibly adjusted according to the application scenario, thus adapting to different application scenarios and supporting scenarios with lower code rate requirements. Furthermore, by avoiding decoding delays caused by non-orthogonal rows in the basis matrix of the NR, decoding latency can be reduced. Simultaneously, it can maintain the good decoding structure and decoding threshold of the original basis matrix, and support lower-complexity decoding and HARQ retransmission.

This invention proposes a fast continuous cancellation decoding method for special nodes of polar codes, comprising: determining special nodes in the target decoding tree for continuous cancellation decoding based on the distribution of polar code information bits and frozen bits, wherein the special nodes include a first dual constraint and a second dual constraint; performing a hard decision on the log-likelihood ratio sequence of the special nodes to obtain a first estimated codeword sequence; calculating the check value of the first dual constraint, and flipping the bit estimates in the first estimated codeword sequence based on the check value of the first dual constraint to obtain a second estimated codeword sequence; calculating the check value of the second dual constraint, constructing a set of flipped bit pairs based on the check value of the second dual constraint, selecting the bit pair with the smallest metric in the set, and flipping the bit estimates at the corresponding positions of the bit pairs in the second estimated codeword sequence to obtain the target estimated codeword sequence. This method significantly reduces decoding latency while maintaining performance lossless and is easy to implement on hardware platforms.

The invention discloses a fast node polarization code decoding method for parity check, and belongs to the field of wireless communication signal processing. According to the method, hardware implementation complexity and decoding delay are comprehensively considered, an existing decoding method is improved on the basis of an SCL decoding algorithm assisted by mixed parity check and CRC, parity check bits are inserted into a sequence, the parity check bits are used for conducting parity check processing on the sequence in a segmented mode, and when a parity check node is decoded during decoding, the sequence is decoded to the CRC node. A path passing the parity check and having the most reliable path metric is reserved among the plurality of paths. Compared with the traditional Polar code decoding algorithm, the method provided by the invention has the advantages that the decoding delay is reduced by utilizing the fast nodes, and meanwhile, the decoding path is segmented by adopting a parity check mode and the segments are pruned, so that the calculation complexity of the decoding algorithm is reduced.

The invention relates to the technical field of computers and data processing, discloses a streaming transmission and low-delay decoding method based on a cloud game, and aims to solve the problems of high transmission delay, low coding and decoding efficiency and split interaction response in the prior art. The method comprises the following steps: extracting dynamic characteristics of a game picture, dynamically adjusting a coding rate and a resolution ratio through a reinforcement learning model based on network state parameters and the dynamic characteristics, generating a current frame prediction result by using an AI prediction model, and preferentially transmitting a key frame patch, decoding is accelerated through a special hardware decoding chip, asynchronous rapid decoding is adopted for key frame patches, and frames and user input events are decoded synchronously to control the end-to-end total delay to be smaller than or equal to 50 ms. According to the technical scheme, the loss rate and the average transmission delay of the key picture area can be remarkably reduced, the decoding delay is reduced, it is ensured that the total delay is stabilized within 50 ms, and the interaction synchronism and the operation response accuracy of the high-speed dynamic game are improved.

Techniques and tools for reducing latency in video encoding and decoding by constraining latency due to reordering of video frames, and by indicating the constraint on frame reordering latency with one or more syntax elements that accompany encoded data for the video frames. For example, a real-time communication tool with a video encoder sets a syntax element that indicates a constraint on frame reordering latency, which is consistent with inter-frame dependencies between multiple frames of a video sequence, then outputs the syntax element. A corresponding real-time communication tool with a video decoder receives the syntax element that indicates the constraint on frame reordering latency, determines the constraint on frame reordering latency based on the syntax element, and uses the constraint on frame reordering latency to determine when a reconstructed frame is ready for output (in terms of output order).

The present application provides a channel encoding or decoding method and a communication apparatus, which enable generation of a new inserted row based on an adjacent row of a base matrix in NR, or generation of a new inserted row based on a certain row in the base matrix in NR, thereby lifting the base matrix in NR. The lifted base matrix can be flexibly adjusted according to an application scenario, thereby being applicable to different application scenarios and being capable of supporting scenarios with lower code rate requirements. In addition, because this prevents decoding stalls caused by non-orthogonal rows in a base matrix in NR, decoding latency is also reduced. At the same time, this also maintains a favorable decoding structure and decoding threshold of the base matrix, and supports lower-complexity decoding and HARQ retransmission.

Techniques and tools for reducing latency in video encoding and decoding by constraining latency due to reordering of video frames, and by indicating the constraint on frame reordering latency with one or more syntax elements that accompany encoded data for the video frames. For example, a real-time communication tool with a video encoder sets a syntax element that indicates a constraint on frame reordering latency, which is consistent with inter-frame dependencies between multiple frames of a video sequence, then outputs the syntax element. A corresponding real-time communication tool with a video decoder receives the syntax element that indicates the constraint on frame reordering latency, determines the constraint on frame reordering latency based on the syntax element, and uses the constraint on frame reordering latency to determine when a reconstructed frame is ready for output (in terms of output order).

The present application provides a channel encoding or decoding method and a communication apparatus, which enable generation of a new inserted row based on an adjacent row of a base matrix in NR, or generation of a new inserted row based on a certain row in the base matrix in NR, thereby lifting the base matrix in NR. The lifted base matrix can be flexibly adjusted according to an application scenario, thereby being applicable to different application scenarios and being capable of supporting scenarios with lower code rate requirements. In addition, because this prevents decoding stalls caused by non-orthogonal rows in a base matrix in NR, decoding latency is also reduced. At the same time, this also maintains a favorable decoding structure and decoding threshold of the base matrix, and supports lower-complexity decoding and HARQ retransmission.

This invention discloses a high-speed satellite communication decoder and decoding method based on an ARM-FPGA hybrid architecture, belonging to the field of satellite communication technology. The invention employs an ARM-FPGA heterogeneous platform to achieve hardware and software collaboration. The software subsystem runs on the ARM and is responsible for packet loss detection and flow control; the hardware subsystem is a freely running decoding IP core on the FPGA, executing a real-time Gaussian elimination algorithm, and using a dual-half-table architecture multiplier and parallel computing module to accelerate Galois domain operations; high-speed data and configuration information interaction is achieved through the AXI4 bus. This decoder distributes latency, reducing the average decoding latency by 57.44%, and increasing throughput to more than twice that of traditional solutions, significantly improving the real-time performance and reliability of satellite communication.

Communication systems that utilize receivers for decoding short block length messages are disclosed. In many embodiments, the receiver includes an antenna for receiving encoded data, via RF signals, a demodulator for obtaining symbols from the RF signal, a demapper for generating symbol metrics, and a parallel list decoder. In several embodiments, the parallel list decoder processes multiple trellis stages simultaneously, enabling efficient decoding of the symbol metrics to obtain received, bits. In certain embodiments, the parallel list decoder divides the decoding trellis into segments, processes these segments independently, and combines them pairwise to form new segments. This parallel processing approach can allow for reduced decoding latency and improved efficiency in handling short block length messages. making it particularly suitable for applications requiring rapid data exchange and low-latency communication.

The invention provides a self-adaptive multi-level coding transmission method and device and electronic equipment. Multi-level coding modulation is carried out at a transmitting end based on a modulation coding scheme identifier according to a pre-constructed offline parameter table. And demodulating and decoding at a receiving end according to the same modulation coding scheme identifier and the corresponding multi-level coding modulation structure. On one hand, the structure retains the capability of an MLC coding modulation structure for finely distributing code rates to match channels, and can realize higher spectrum efficiency compared with a BICM coding modulation architecture. And on the other hand, when a receiving end demodulates and decodes, the multi-level coding structure has the characteristic of local parallelism, so that the time delay of demodulation and decoding can be reduced, and the defect of low throughput rate of an MLC coding modulation structure is improved to a certain extent.

Methods and devices are provided for reducing the decoding latency introduced by LMCS. In one method, during the decoding of an encoding unit (CU), a plurality of reconstructed luminance samples is selected from a first predetermined region adjacent to a second predetermined region where the CU is located, an average of the plurality of reconstructed luminance samples is calculated, and the average of the plurality of reconstructed luminance samples is used directly, without any clipping, in deriving a residual chrominance scaling factor to decode the CU.

Embodiments of the invention relate to a network access node (100) and a client device (300) employing assistance resource set associated with a search space and decoding information in communication systems. Thus, a network access node (100) transmits a first control message (510) in at least one assistance resource set to at least one client device (300). The assistance resource set is associated with at least one search space, and wherein the first control message (510) indicates a decoding information for decoding a downlink control information in at least one control resource set associated with the search space. The client device (300) uses the decoding information for decoding the downlink control information received in the control resource set associated with the search space. Thereby, the decoding of the downlink control information is simplified implying among other things reduced decoding latency and power consumption. Furthermore, the invention also relates to corresponding methods and a computer program.

This application provides a decoding method, chip, and related apparatus. By introducing a threshold judgment mechanism, the controller chip can simultaneously calculate the number of bits that do not satisfy the parity check equation and perform the bit flipping process, reducing the decoding latency of the controller chip and improving the decoding throughput. Simultaneously, the algorithm for calculating the number of bits that do not satisfy the parity check equation for each bit is optimized, reducing the probability of correct bits being incorrectly flipped, thereby reducing the error plane in the decoding.

The invention discloses a multi-strategy hard decoding method applied to a middle-screen video call. The method comprises the following steps: analyzing an FU Indicator and an FU Header of an RTP packet based on an FU-A packaging structure, extracting Start and End flag bits, establishing an intra-frame RTP packet fragment reconstruction window, detecting sequence continuity through an RTP sequence number, recombining a complete NALU or marking damage; analyzing an NALU head Type field, identifying a frame type and a GOP structure, constructing a reference frame index chain, recording a forward reference frame dependency relationship, judging a risk NALU, and dividing a compensable NALU and a discarded NALU based on an I frame and P frame association model; and executing a fault-tolerant strategy according to the damage information and the compensable and lost judgment result. According to the method, high-quality video call with decoding delay can be realized on low-computing-power medium-screen equipment, and the problems of video lagging and blurred screen caused by network fluctuation can be effectively solved.

The application discloses a special accelerator for a hierarchical greedy decoding algorithm, and belongs to the technical field of quantum computation, and comprises a transformation unit, a decoding core and a permutation unit; the transformation unit is used for receiving original error symptoms, and multiplying the original error symptoms with a transformation matrix through sparse matrix vector multiplication to generate transformed error symptoms; the decoding core is used for executing a hierarchical greedy decoding algorithm, dividing error patterns into left errors and right errors, and performing calculation including guessing right errors and decoding left errors in parallel based on the transformed error symptoms to obtain new values of the error patterns; and the permutation unit is used for receiving the new values of the error patterns, multiplying the new values of the error patterns with a permutation matrix through sparse matrix vector multiplication to calculate final error patterns. The application can realize real-time qLDPC decoding and significantly reduce decoding delay.

This application proposes a polar code rate-sequence node decoding method based on a minimum combination set, comprising: offline construction of minimum combination sets for SPC nodes and R1 nodes; obtaining the received sequence of the polar code to be decoded, and calculating the LLR of the internal source nodes based on the obtained LLR of the SR1 nodes; calculating the corresponding maximum likelihood estimated codewords based on the LLR of the source nodes, and using the codewords to apply parity check constraints to the root node, splitting the root node into multiple SPC nodes; obtaining the flipped combination set of each split SPC node, and selecting candidate flipped combinations based on the path metric increment; performing a union operation on the candidate flipped combinations to construct a new set, and selecting new candidate flipped combinations from the new set based on the minimum combination set of the R1 nodes; flipping the new candidate flipped combinations to obtain candidate paths and corresponding path metric values ​​as the decoding results of the SR1 nodes. This invention, employing the above scheme, significantly reduces the decoding latency and complexity of the SR1 nodes.

Methods and devices for reducing decoding latency introduced by LMCS are provided. In one method, during decoding of a coding unit (CU), a plurality of reconstructed luminance samples are selected from a first predetermined region, the first predetermined region is adjacent to a second predetermined region where the CU is located, the average of the plurality of reconstructed luminance samples is calculated, and when deriving a chroma residual scaling factor for decoding the CU, the average of the plurality of reconstructed luminance samples is used directly without any clipping.

Methods and devices are provided for reducing the decoding latency introduced by luma mapping with chroma scaling (LMCS). In one method, during decoding of a coding unit (CU) that is coded by an inter mode or Combined Inter and Intra Prediction (CIIP) mode under LMCS framework, a plurality of reconstructed samples of luma component is obtained in a mapped domain, a plurality of converted samples of luma component is obtained in an original domain by converting the plurality of reconstructed samples of luma component from the mapped domain into the original domain, and the plurality of converted samples of luma component is used in the original domain, without clipping, in deriving chroma scaling factors for decoding the chroma samples of the CU.

The invention discloses a DNN intelligent communication system and method based on an SBMA scheme. The system comprises a base station and a terminal. The base station is configured to pre-process information needing to be received by a user so as to convert the information into a bit vector suitable for an antenna; performing SCMA coding on the bit vector to obtain a superposed codeword vector; performing symbol reconstruction on the superposed codeword vector, and converting the superposed codeword vector into an emission vector corresponding to each subcarrier; and carrying out BIA coding on the transmission vector so as to send the transmission vector to the terminal of the user. The terminal is configured to: process a received signal based on a BIA decoding matrix to cancel multi-user interference; performing zero-forcing decoding on the signal after eliminating the multi-user interference to obtain an estimated emission vector of a terminal of each user; performing symbol reconstruction on the estimated emission vector to obtain an estimated superposition codeword vector of the terminal on the antenna; and performing DNN decoding on the estimated superposed codeword vector to obtain an estimated bit vector. According to the invention, the decoding delay is lower, and the environment self-adaptive capability is higher.

The invention discloses an STE high-speed decoding device and system for realizing autonomous and controllable domestic computing power, and solves the problems of monopoly, low decoding efficiency and poor safety controllability of an overseas computing power architecture. According to the invention, domestic hardware is used as a base, an STE high-speed decoding core unit is integrated, and based on STE coding rules and proportional philosophy, parallel layered decoding, dynamic computing power scheduling and national security level security verification are adopted, so that a decoding rate greater than or equal to 10 bit / s is realized. A special hardware instruction set is expanded at a chip end, and the ST-ALU and the cache are integrated, so that the decoding delay is greatly reduced; and the AI large model end realizes inference decoding lossless restoration and full-link credible verification, and eliminates distortion and security risks. The method is autonomous, controllable, high in speed, low in time delay, high in safety and suitable for national computing power infrastructure, AI large model deployment and high-performance computing, and the domestic computing power competitiveness and the safety guarantee capability can be remarkably improved.

Techniques and tools for reducing latency in video encoding and decoding by constraining latency due to reordering of video frames, and by indicating the constraint on frame reordering latency with one or more syntax elements that accompany encoded data for the video frames. For example, a real-time communication tool with a video encoder sets a syntax element that indicates a constraint on frame reordering latency, which is consistent with inter-frame dependencies between multiple frames of a video sequence, then outputs the syntax element. A corresponding real-time communication tool with a video decoder receives the syntax element that indicates the constraint on frame reordering latency, determines the constraint on frame reordering latency based on the syntax element, and uses the constraint on frame reordering latency to determine when a reconstructed frame is ready for output (in terms of output order).

The present application discloses a method and system for generating a check matrix for a one-correction, two-check-correction adjacent code, the method comprising: obtaining an initial check bit number based on the number of input data bits; constructing an odd-weight vector pool based on column vector weights and performing a variable initialization process; calculating a layer depth based on the odd-weight vector pool and a heuristic search; obtaining a feasible vector sequence from the odd-weight vector pool to the layer depth through a Monte Carlo random method in parallel search; constructing a target check matrix by using A* search in the feasible vector sequence; judging whether the target check matrix has been constructed; and performing even-weight vector replacement optimization on the target check matrix; the method can generate a corresponding check matrix, and combined with the Monte Carlo random method and the A* heuristic search, achieves a balanced optimization between the number of check bits and the check matrix row weights, substantially reducing hardware overhead and required bit width; and substantially reducing encoding and decoding delays and delay differences between different encoding and decoding paths.

Communication systems that utilize receivers for decoding short block length messages are disclosed. In many embodiments, the receiver includes an antenna for receiving encoded data, via RF signals, a demodulator for obtaining symbols from the RF signal, a demapper for generating symbol metrics, and a parallel list decoder. In several embodiments, the parallel list decoder processes multiple trellis stages simultaneously, enabling efficient decoding of the symbol metrics to obtain received, bits. In certain embodiments, the parallel list decoder divides the decoding trellis into segments, processes these segments independently, and combines them pairwise to form new segments. This parallel processing approach can allow for reduced decoding latency and improved efficiency in handling short block length messages. making it particularly suitable for applications requiring rapid data exchange and low-latency communication.

This invention provides a communication and control method for aircraft in blackout environments, relating to the fields of extreme environment communication, anti-jamming communication, and guidance and control technology for hypersonic aircraft. It employs an integrated architecture of low-bandwidth simplified signal transmission, local fast decoding, and adaptive execution of pre-stored commands. A standardized maneuver control command library is pre-stored locally on the aircraft. The ground only transmits simplified coded signals containing command numbers. After transparent forwarding by relay nodes, the signal processing and command mapping are completed by the aircraft's local fast decoding unit, directly executing the pre-stored commands, thus eliminating reliance on broadband real-time communication and remote ground computing. This invention supports multi-band, multi-modulation adaptive matching to plasma sheath environments, with a decoding latency ≤1ms and a blackout penetration success rate ≥99%. It enables highly reliable, low-latency, and highly anti-jamming real-time maneuver control of aircraft in blackout environments, and is adaptable to various carriers such as hypersonic aircraft, reentry capsules, and rocket boosters.