Implementation method of high-speed reed-solomon (RS) codec based on field programmable gate array (FPGA)

An implementation method and codec technology are applied in the field of FPGA-based high-speed RS codec implementation, and can solve the problems of difficulty in achieving decoding speed, complex implementation, and high engineering implementation cost.

Inactive Publication Date: 2011-07-13
XIDIAN UNIV
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Problems solved by technology

[0004] In the decoding process of RS codes, due to the solution of the key equations in the decoding method, the method of multiple iterations is adopted, the implementation itself is more complicated, and because the engineering realization of the decoding method is also mo

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  • Implementation method of high-speed reed-solomon (RS) codec based on field programmable gate array (FPGA)
  • Implementation method of high-speed reed-solomon (RS) codec based on field programmable gate array (FPGA)
  • Implementation method of high-speed reed-solomon (RS) codec based on field programmable gate array (FPGA)

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Embodiment Construction

[0096] In order to make the technical means, creative features and objectives of the present invention easy to understand, the present invention is further described below in conjunction with specific embodiments.

[0097] A kind of FPGA-based high-speed RS codec realization method of the present invention comprises the FPGA realization of high-speed RS (244,212) encoder and the FPGA realization of high-speed RS (244,212) decoder, adopts reverse clock to accomplish.

[0098] The FPGA method to realize the high-speed RS (244, 212) encoder is as follows:

[0099] Described high-speed RS (244, 212) coder adopts dual-clock driving mode work, for each group of 212 information symbol {m 1 , m 2 , L, m 212} encoding to get 32 ​​check code elements {p 1 ,p 2 , L, p 32}, without increasing the complexity of the hardware, the clock utilization rate is improved, thereby improving the encoding speed, and the resource consumption is low, such as figure 1 , the specific implementatio...

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Abstract

The invention discloses an implementation method of a high-speed reed-solomon (RS) codec based on a field programmable gate array (FPGA), comprising FPGA implementation of a high-speed RS (244, 212) coder and FPGA implementation of a high-speed RS (244, 212) decoder. In the invention, the high-speed RS coder is a circuit based on polynomial division, and the high-speed RS decoder is based on three-level pipeline architecture, and dual-clock driving based on clock i_clk and reverse clock i_clk180 is adopted; In addition, based on a common Galois field (GF) multiplying unit, three basic computing units, including a constant coefficient GF multiply-add fused unit, a constant coefficient GF multiplying unit and a dual-clock period controlled GF multiplying unit are provided, thereby greatly improving the computing speed and reducing hardware complexity. The implementation method has the advantages of high supporting throughput rate and strong capacity of correcting burst errors and can be applied to many aspects.

Description

technical field [0001] The invention belongs to the field of channel encoding and decoding devices in communication, and in particular relates to an FPGA-based high-speed RS (244, 212) encoding and decoding implementation method that can be used for satellite high-speed signal processing. Background technique [0002] RS code, constructed in 1960 by Reed and Solomon using Mattson-Solomon (MS) polynomial, is a kind of multi-ary BCH code with strong error correction ability, which can correct both random errors and burst errors. This good characteristic makes it especially suitable for communication systems with very complex channel interference. The so-called complex channel interference refers to the fact that the error type in the channel may be a burst error or a random error at a certain moment, but there can only be one type of error at a certain moment. The RS code is not only a good code for correcting random errors, but also a code that is close to the best for corre...

Claims

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Application Information

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IPC IPC(8): H03M13/15H04L1/00
Inventor 宫丰奎彭克蓉葛建华
Owner XIDIAN UNIV
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