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High-speed coding chip

A decoding chip, high-speed technology, applied in the field of decoding chips, can solve the problems of complex decoding methods, difficult to achieve decoding speed, high engineering cost, etc.

Inactive Publication Date: 2006-10-04
NAT SPACE SCI CENT CAS
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, due to the characteristics of the RS code itself, the decoding method itself is relatively complicated, and the engineering implementation of the decoding method is also relatively difficult, resulting in high engineering costs and difficulty in achieving the ideal decoding speed.

Method used

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Experimental program
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Embodiment 1

[0080] The various parameters that embodiment adopts are as follows:

[0081] m=8, representing the number of bits required for a code symbol of an RS code;

[0082] E=16, the code block that represents an RS code can correct the number of error code symbols;

[0083] Among them, m and E are mutually independent parameters.

[0084] N=2 m -1=255, representing the number of code symbols of the code block of each RS code;

[0085] 2E=32, representing the number of code symbols of the parity bit in the code block of each RS code;

[0086] k=n-2E=223, representing the number of code symbols of the information bits in the code block of each RS code;

[0087] F(X)=X 8 +X 7 +X 2 +X+1, indicating that the code symbol of the RS code is in GF(2 8 ) The domain generator polynomial defined in );

[0088] g ( x ) = Π j = 112 ...

Embodiment 2

[0197] Such as Figure 8 As shown, on the basis of Embodiment 1, a de-interleaving circuit 6 connected to the data input circuit 1 is also included for correcting burst errors. The RS code data is first input to the de-interleaving circuit 6 for de-interleaving, and then the processed data is input to the data input circuit 1, and then the decoding process as described in the first embodiment is performed.

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Abstract

The invention relates to a RS code decoding chip which coincident CCSDS standard. The decoding chip comprises a stagger-resolving circuit, a data input circuit, a computing syndrome circuit, a computing key equation circuit, a money search circuit, an error value capture circuit, an error correct circuit and a time delay circuit, wherein the computing key equation circuit computes the error position polynomial and error value polynomial needed by the decoding course by the captured syndrome and RiBM analog; the error value capture circuit computes the error value of the input data by the deformation Forney analog and output it; each part of the computing circuit adopts finite field to do basic analog circuit, which comprises a finite field addition computing circuit, a finite field multiply computing circuit and finite field division computing circuit.

Description

technical field [0001] The invention relates to a decoding chip, in particular to a high-speed RS (Reed-Solomon referred to as RS) code decoding chip conforming to the CCSDS (Consultative Committee for Space Data Systems, referred to as CCSDS) standard and used in deep space exploration. Background technique [0002] The CCSDS standard defines channel coding for the protection of space telemetry and engineering data in deep space exploration. This standard defines the field generator polynomial and code generator polynomial of (255, 223) RS codes commonly used in deep space exploration. In deep space exploration, it is often necessary to transmit a large amount of precious telemetry data and engineering data, or to transmit clear dynamic image data in real time. The reliability of the transmitted data can be ensured by using the RS error-correcting code technology conforming to the CCSDS standard. However, due to the characteristics of the RS code itself, the decoding meth...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04L1/00H03M13/15
Inventor 陈晓敏张玉良石俊峰孙辉先
Owner NAT SPACE SCI CENT CAS
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