Error burst detection for assessing reliability of a communication link

Abstract

Methods, apparatus, and systems for preventing false packet acceptance in high-speed links. In accordance with one aspect, embodiments are disclosed that facilitate assessing the probability of error bursts in receivers that include decision feedback equalizers (DFEs) and that perform non-contiguous mapping of received bits to frame bits. From this probability, calculation of a mean-time to false packet acceptance (MTTFPA) may be determined, and indication that a projected link MTTFPA is too low can be used to trigger an alert or invoke some safety mechanism. Associated operations may then be performed to ensure the link is prevented from being operated in an unsafe condition under which false packet acceptance may occur.

Description

CROSS-REFERENCE TO RELATED APPLICATION[0001]This application claims the benefit of the filing date of U.S. Provisional Application No. 61 / 889,945, filed Oct. 11, 2013, entitled “ERROR BURST DETECTION FOR ASSESSING RELIABILITY OF A COMMUNICATION LINK” under 35 U.S.C. §119(e). U.S. Provisional Application No. 61 / 889,945 is further incorporated herein in its entirety for all purposes.BACKGROUND INFORMATION[0002]An important feature of network communication is data integrity. Under Ethernet, for example, this is accomplished using a 32-bit Cyclic Redundancy Check (CRC32) field that is added to each Ethernet MAC (Media Access Control) frame. The CRC provides full protection against many types of errors, including up to 3 bit errors in a normal-size MAC frame and bursts of consecutive errors up to 32 bits long. Other combinations of errors may pass the CRC32 check with a small probability (up to 2̂-32 for random error distribution).[0003]If multiple errors occur on an Ethernet link, the M...

AI Technical Summary

Benefits of technology

The patent text describes a method for detecting errors in a communication link using a combination of error detection and error correction techniques. The method involves adding a cyclic redundancy check (CRC) to each Ethernet frame to detect errors caused by bursts of errors. The CRC is a 32-bit value that is added to the frame and ensures that errors are detected and addressed. The method also includes using a decision feedback equalizer (DFE) to reduce the likelihood of errors, but this can introduce error propagation. By mapping physical bits to contiguous bits in a frame and using alignment markers, the method ensures that errors are detected and addressed quickly to prevent false packet acceptance. The technical effect of the patent text is to provide a reliable and efficient method for detecting and addressing errors in high-speed communication links.

Problems solved by technology

A DFE is helpful in reducing the probability of individual errors, but can introduce error propagation: once a bit is incorrectly decoded (a bit error occurs), it is more likely that the next bit will also be incorrectly decoded (the error will propagate).

However, newer encoding schemes require striping data bits across several lanes, and un-striping the physical lane bits back at the receiver.

As a result, physical lane bits are mapped to frame bits in a non-contiguous way, and a burst is converted into a series of non-adjacent errors, against which the CRC does not protect perfectly.

Statistical calculations show that with bit-muxing, error bursts may degrade MTTFPA to intolerable periods (thousands of years) unless they have sufficiently low probability.

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