8 results about "Wire protocol" patented technology

This application discloses a switch control circuit based on a single-wire protocol power supply. The circuit includes: a switch module for receiving switch control signals sent by a control switch module, and turning the switch on or off according to the switch control signals; a high / low level control module for receiving level control signals sent by the control switch module, and sending high and low levels externally according to the level control signals; a control switch module for sending level control signals to the high / low level control module, sending switch control signals to the switch module, and receiving data reception signals sent by the slave chip; and a power supply module for providing voltage to the slave chip, and for charging the slave chip through the switch module when the single-wire communication interface is at a high level. Thus, by precisely controlling the on / off state of the switch module through the control switch module, the internal power consumption of the slave chip is reduced, ensuring the normal operation of the slave chip, and preventing charge leakage from the slave chip's power supply.

This application discloses a bidirectional communication system and method for board daisy chain based on a single-wire protocol, relating to the field of computer technology. This application constructs a single-bit serial protocol daisy chain system without an independent clock line, employing dual single-wire directed links or a single half-duplex shared link to achieve bidirectional transmission between boards. This significantly reduces the hardware connection harness and input / output resource usage, lowers connector and line costs, and is suitable for scenarios involving large-scale, low-cost board cascading. After power-on, master-slave identification is automatically completed based on the upstream valid frame reception status, avoiding conflicts between multiple master nodes without the need for preset DIP switches, configuration files, or external addressing commands. The motherboard uses a preset default address, and the slave boards use an allocation method where the upstream address is incremented hop by hop, ensuring a strict correspondence between physical cascading positions and logical addresses. This achieves automatic convergence with zero manual address configuration, improving system deployment and maintenance efficiency.

Disclosed is an apparatus for enabling wireless transmission of a signal transmitted via a wire between a host device and a peripheral device. The apparatus comprises a physical layer module configured for detecting the signal between the host device and the peripheral device. The signal follows a wired protocol. The apparatus comprises a programmable module configured for decoding the signal following the wired protocol. The apparatus comprises a processing module configured for extracting data from the signal following the wired protocol. The processing module is configured for modifying the signal to follow a wireless protocol. The apparatus comprises a wireless transmission module interconnected with an antenna. The antenna is configured for electromagnetic field emission. The wireless transmission module is configured for transmitting the signal according to the wireless protocol. The apparatus is configured for intercepting the signal between the host device and the peripheral device using high impedance sensing.

This invention relates to the field of digital information transmission technology and discloses a four-way protocol conversion method for photovoltaic equipment, comprising: an Ethernet control chip receiving the original protocol message of the photovoltaic power station and writing it into the source protocol receive buffer; using a memory offset pointer to match the message delimiter to determine the dynamic byte offset of the payload data; constructing a three-segment descriptor chain based on the offset, including the physical base address of the target protocol header, the physical base address of the payload data, and the base address of the checksum; and a distributed direct memory access controller extracting and aggregating heterogeneous data across physical memory pages according to the descriptor chain to generate continuous target protocol frames. This invention uses data pointer routing to replace byte copying, eliminates the physical reassembly process at the end of the protocol conversion, reduces the transmission latency of concurrent scheduling instructions, ensures the exchange efficiency of heterogeneous digital information streams, and enhances the response performance of the station-end communication system.

The invention relates to an intelligent power management integrated circuit with AI dynamic adjustment and multi-mode cooperation and a control method thereof, and belongs to the field of power management integrated circuits, the intelligent power management integrated circuit comprises an AI dynamic adjustment module, a multi-protocol adaptive charging system and a three-dimensional heterogeneous packaging structure, the AI dynamic adjustment module comprises a hybrid neural network architecture and a federated learning framework, the multi-protocol self-adaptive charging system integrates a PD 3.1 EPR wired protocol control unit, a Qi v2.0 wireless charging driving module and a dynamic impedance matching circuit, and the three-dimensional heterogeneous packaging structure comprises a TVS (Transient Voltage Suppressor), a micro-channel heat dissipation unit and a FeRAM (FeRAM) storage unit. According to the invention, an AI dynamic adjusting system, a multi-protocol adaptive charging system, a three-dimensional heterogeneous packaging framework and a self-powered safety system are added, so that a novel AI intelligent power management chip which is low in power consumption, intelligent and small in size is truly realized.

The present invention relates to the field of electrical signal transmission, and discloses a two-wire protocol sending circuit and a two-wire transmitter. The circuit includes: a first amplifier, a resistor, a first transistor, and a second transistor; the positive input terminal of the first amplifier is connected to the first end of the resistor, the second end of the resistor is grounded, the output terminal of the first amplifier is respectively connected to the first ends of the first transistor and the second transistor, the second end of the first transistor is connected to the first end of the resistor, the third end and the second end of the second transistor are respectively connected to a receiving unit through the positive terminal and the negative terminal of an external loop, and the third end of the first transistor, the third end of the second transistor, and the power supply terminal of the first amplifier are all connected to the power supply voltage terminal of the circuit; by adjusting the ratio of the number of the second transistor to the first transistor, a control current signal of 4-20 mA is controlled to be output by the circuit, and compared with the control method and circuit structure of a traditional typical circuit, it is simpler, reduces the chip area, and is beneficial to reducing the chip manufacturing process cost.

A single-wire protocol method comprises: inputting (X1+M1) pulses through a single-wire bus according to a pulse definition table, where M1 is less than or equal to 2A1; and after inputting the (X1+M1) pulses, inputting (Y1+N1) pulses through the single-wire bus according to the pulse definition table, where N1 is less than or equal to 2B1, the (M1+N1) pulses are utilized to set a first output voltage, and the first output voltage has at most (2A1×2B1) voltage levels based on A1 and B1. By dividing the first output voltage into two parts, it is capable of reducing a write time of a voltage setting instruction.

The application discloses a method and a communication system compatible with one-wire communication and I2C communication, and belongs to the technical field of communication. The method compatible with one-wire communication and I2C communication comprises the following steps: if the communication system runs in a one-wire protocol mode, a master device communicates with a slave device connected with the IO port based on a one-wire communication protocol through the IO port; and if the communication system runs in an I2C protocol mode, the master device selects the slave device capable of communicating with the master device by controlling the potential of the IO port, and the master device communicates with the slave device based on an I2C communication protocol through an I2C bus. The technical scheme provided by the embodiment can effectively improve the compatibility of the communication system, and can effectively reduce the product development cost and the cost of the communication system without developing and configuring different versions of chips in the device for different protocols.