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Floating point multiplier-adder

A floating-point multiplier and adder technology, which is applied in the fields of instrumentation, calculation, and electrical digital data processing.

Pending Publication Date: 2022-07-12
江苏华创微系统有限公司 +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0002] In high-performance DSP at present, floating-point multiply-adder is an important part of realizing high-performance computing, and the technology related to the present invention has floating-point multiplier, floating-point adder, floating-point multiply-adder etc., in existing technology Some of them only support single-precision calculations, some have low operating frequency, some have too many pipeline stages, some do not support denormalized numbers, and some have too bloated structures and poor timing, etc.

Method used

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Embodiment Construction

[0037] The technical solutions of the present invention are described in detail below, but the protection scope of the present invention is not limited to the embodiments.

[0038] In order to make the content of the present invention more obvious and easy to understand, the following is combined with the appendix figure 1 -Attached Figure 5 and specific implementations for further description.

[0039] In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention, but not to limit the present invention.

[0040] like figure 1 As shown, a floating-point multiplier-adder proposed by the present invention realizes the floating-point multiply-add operation in the form of A*B+C. The floating-point m...

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Abstract

The invention discloses a floating-point multiply-add device, which realizes floating-point multiply-add operation in a form of A * B + C. The floating-point multiply-add device adopts a three-stage pipeline mode to realize the floating-point multiply-add operation, completes floating-point multiplication in a first pipeline beat, completes addition in a second pipeline beat and completes rounding operation and exception judgment in a third pipeline beat, and outputs a final result. The floating-point multiply-add device has the advantages that single-double-precision floating-point number multiply-add operation is achieved, and a three-level assembly line framework of non-normalized numbers is supported.

Description

technical field [0001] The invention relates to the technical field of chip design, in particular to a floating-point multiplier-adder. Background technique [0002] At present, floating-point multiplier-adder is an important part of realizing high-performance computing in high-performance DSP. The technologies related to the present invention include floating-point multiplier, floating-point adder, floating-point multiplier-adder, etc. In the existing technology Some of them only support single-precision operations, some run at low frequency, some have too many pipeline levels, some do not support denormalized numbers, and some are too bloated and have poor timing. SUMMARY OF THE INVENTION [0003] The present invention proposes a floating-point multiplier-adder, and the adopted technical scheme is: [0004] A floating-point multiplier-adder, which realizes the floating-point multiply-add operation in the form of A*B+C. The floating-point multiplier-adder uses a three-st...

Claims

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Application Information

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IPC IPC(8): G06F7/487G06F7/544G06F7/57
CPCG06F7/5443G06F7/4876G06F7/57
Inventor 王嗣茗杨思博李明李世平郝明
Owner 江苏华创微系统有限公司
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