39 results about "48-bit" patented technology

An encryption device eliminates data contention and minimizes area by accessing twice data for a given time by using a memory device of two times faster access time. The encryption device for performing encryption of plain text blocks using data encryption standard algorithm, wherein the encryption device includes an initial permutation unit, a data encryption unit having n-stage (n is an even number) pipeline structure using a first clock, a second clock and a third clock, and an inverse initial permutation unit, the encryption device includes: a multiplexer for selecting one of n/3 48-bit inputs; 8 S-Boxes, each for receiving 6-bit address among the selected 48-bit and outputting 4-bit data; a demultiplexer for distributing 32-bit data from the S-Boxes to n/3 outputs; and a controller for control the multiplexer and the demultiplexer with a fourth clock and a fifth clock, wherein the fourth and the fifth clock are faster than the first, the second and the third clocks by n/3 times.

The invention discloses a digital image encrypting and decrypting method comprising the following steps of: appointing the gray value range of an encrypted image according to an image to be encrypted; dividing the image to be encrypted into pixel blocks with the same size, and computing a pixel mean value by virtue of a formula; generating a sub-secret key according a 48-bit binary system key stream preset by a user, and building Logistic mapping according to the pixel mean value; converting into a binary sequence according to the number of floating points generated by the Logistic mapping, and taking the binary sequence as the sub-secret key of the next pixel block; scrambling the pixel in each pixel block based on the improved Arnold conversion, and combining the scrambled pixel blocks into a matrix; and replacing the adjoining pixels in the matrix, so that a ciphertext image can be formed. According to the requirement of a user, the image can be encrypted by means of different numbers of sheaves, various filtering attacks can be resisted, and the invariability of the pixel mean value of the image can be realized, so that the whole style and feature of the original image can be maintained.

The invention relates to a 32 bits microprocessor and its instruction set. The microprocessor system comprises an instruction processor, a control component, a fixing point operation a floating-point operation, a register group, a storage interface component and an I/O processor. The entire instruction cycle adapts two state pipelining and is simple in structure. The system is provided with 16 32 bits general registers which hold 4GB storage address space and input output address space. The storage, the I/O processor and the central processor are connected with 64 bits data path. The speed of the processor can be up to 32 bits instruction flow and 32 bits data flow in each clock cycle. The microprocessor system supports 16 bits, 32 bits and 48 bits three instruction formats which are nine kinds and 50 instructions, wherein, the floating-point add, subtract, multiply and divide, fixing-point divide, fixing-point modulus, the conversion between floating-point and fixing-point are all realized by instructions. The instruction is simplified in number but is strong in function, and also has advantages of RISC and CISC.

The number of MAC addresses and corresponding tables that need to be stored to forward messages in a network is substantially reduced. Conventional MAC addresses are converted to translated (sometimes called “virtual”) MAC addresses using a new hierarchical format which redefines the conventional 48-bit, MAC label. Though the MAC label is redefined the packet size remains the same. For example, the number of MAC address tables stored by a HUB node may be reduced from 60,000 to 8 while the number stored at a POP node may be reduced from 120,000 to 8 in a “flat” Ethernet design.

The invention discloses a special double-pipeline RISC instruction system. The system is provided with two pipelines which are parallel mutually, and sequentially includes an instruction fetching unit, an instruction decoding unit, an instruction execution unit, a memory accessing unit and a data writing back unit. The system uses a double pipeline RISC instruction which comprises two incorporate single pipeline instructions. The invention further provides an operation method of the special double-pipeline RISC instruction system. The method includes the following steps: two parallel pipelines are arranged, namely, the instruction fetching unit, the instruction decoding unit, the instruction execution unit, the memory accessing unit and the data writing back unit are sequentially arranged; the double pipeline RISC instruction provided with two incorporate single pipeline instructions is arranged. Using the invention, the resource waste is avoided, wherein the resource waste is caused because a plurality of resources are not used during implementing algorithms when using a general digital signal processor. In addition, the invention has the advantages that the calculation more than 24 bits (48 bits inside) is realized, at the same time, the cost is low, and the power consumption is low.

The invention provides an information encryption method and an information encryption device used for a mobile terminal and the mobile terminal. The information encryption method comprises the steps that plaintexts requiring encryption are grouped in a way that each group includes 32 bits of plaintexts; initial permutation processing is performed on each group of data after grouping so that the order of all groups of data is arranged again, and secret key permutation processing is performed on preset 48 bits of secret keys so that multiple sub-keys are generated; product transformation processing is performed according to the multiple sub-keys and each group of data after initial permutation processing so that the data after transformation processing are obtained; and inverse initial permutation is performed on the data after transformation processing so that a ciphertext of 32 bits is obtained. According to the technical scheme, the burden of computation of data encryption can be obviously reduced under the premise of guaranteeing security of data encryption so that efficiency of data encryption can be enhanced, and power consumption of the mobile terminal in data encryption can be reduced.

A graphics system coalesces Z data and color data for a raster operations stage. The Z data and color data are stored in a memory aligned tile format. In one embodiment, rendering modes in which the tile does not have a data capacity corresponding to Z data or color data for a whole number of pixels have data for at least one pixel split across entries to improve packing efficiency. Rendering modes having a number of bits for Z data or color data that does not equal a power of two such as 24 bits, 48 bits, and 96 bits, may be implemented with a high packing efficiency in tile formats having a data capacity corresponding to a power of 2 bits.

The invention provides a reconfigurable fixed/floating point general adder. The general adder comprises a 48-bit fixed point adder, a selector and a fixed/floating point operation converter, wherein the 48-bit fixed point adder performs fixed point additive operation and can be reconfigured into a single-precision floating point adder; the selector selects a corresponding fixed point or floating point additive operation passage according to top configuration information and performs output control; and the fixed/floating point operation converter converts the 48-bit fixed point adder into a 32-bit single-precision floating point adder. The general adder has the advantages that a full running structure is adopted, the fixed point adder is correspondingly optimized based on a parallel prefix adder, and on the basis of guaranteeing the operation performance of the fixed point adder, operation delay of the fixed point adder is shortened, and a gate circuit area is reduced. Through the overall structure of the fixed/floating point general adder, the universality of the adder is effectively improved under the condition that precision and data throughput are guaranteed.

A customized Bluetooth enabled identification device for Bluetooth based identification, communication and tracking system is described. The device uses a customized Bluetooth hardware as identification of location is done through its 48 bit unique hardware address by providing password based security over identification.

The invention discloses a special arithmetic logic unit (ALU), comprising 12 48-bit arithmetic or logic modules of a summer, a subtracter, a multiplier (1), a multiplier (2), a divider, logarithm int, a multiplier (3), a multiplier (4), using absolute value, an anti-creeper, taking positive number, taking negative number. The special arithmetic logic unit (ALU) is operated by instructions the length of which is 27 bits including 5 bits for opecode, 6 bits for source 1 address, 6 bits for source 2 address and 10 bits for destination address. Each instruction corresponds to an arithmetic or logic operation. ALU can realize the functions required for electric energy meter design by means of external program, particularly for multi-functional high-performance electric energy meter design, with a simple structure and a high speed.

The invention relates to a method for OFDM system to transmit and receive frame prefix. The transmitting method includes that: a base station firstly assembles frame prefix information into package, so as to obtain original 24 bits; then additional 24 bits are calculated and forms 48 bits required by frame prefix coding with the original 24 bits; coding, modulating and four times repetition are carried out on the bit stream of the 48 bits, and the 48 bits are mapped into four sub channels to be transmitted; the receiving method includes that: a receiving terminal firstly extracts corresponding data in four channels, and demodulating, decoding and de-interlacing are carried out on the data to obtain bit stream of the 48 bits; then verification 24 bits are calculated; the verification 24 bits are compared with the rear 24 bits of the 48 bits, if coincident, decoding is correct, frame configuration information is reported to high layer; or else, decoding is error, and an error message isreturned to the base station. The invention can save system soft hardware resource while the receiving terminal analyzes error.

Embodiments of the present invention provide for implementation of data transfers in an efficient manner. The 48-bit LBA mechanism requires two sets of I/O writes to IDE registers on primary channel or secondary channel. The two sets of I/O writes to the primary or secondary channel registers are performed by setting a status register to a first or second state appropriately depending on the data. Embodiments of the present invention provide a single set of writes to I/O registers when the size of the data transfer is equal to or below a threshold value.

Internet Protocol version 6 (IPv6) network device discovery techniques are disclosed. In some embodiments, IPv6 network device discovery includes determining a route entry (e.g., selecting a first route entry that is less than 126 bits and greater than 48 bits) of a route entry table of a seed device (e.g., a router, such as a well connected router); converting the route entry to an anycast address; and sending a probe to the anycast address. For example, using various techniques described herein, an Internet Control Messaging Protocol (ICMP) probe, for example, with incrementing hop count and the subnet-router anycast addresses as targets can be used to fully discover network devices on an IPv6 network.

First, the method calculates intermediate quantity MK,MK=KNID according to formula, where K is cipher key shared by home network and user, NID is as ID of service network with length equal to 128bit. When service network is circuit-switching domain, lower 40 bit of NID are location area indication LAI, and higher 88 bit are zero. When service network is packet switching domain, lower 48 bit of NID are route area indication RAI, and higher 80 bit are zero. Then, using f1 algorithm calculates MAC in AUTH being as one of quintuple of UMTS authentication vectors. The invention can raise security intensity of UMTS network access authentication, being suitable to third generation of mobile communication system.

The 64-bit single cycle fetch method described here relates to a specific ‘megastar’ core processor employed in a range of new digital signal processor devices. The ‘megastar’ core incorporates 32-bit memory blocks arranged into separate entities or banks. Because the parent CPU has only three 16-bit buses, a maximum read in one clock cycle through the memory interface would normally be 48-bits. This invention describes an approach for a fetch method involving tapping into the memory bank data at an earlier stage prior to the memory interface. This allows the normal 48-bit fetch to be extended to 64-bits as required for full performance of the numerical processor accelerator and other speed critical operations and functions.

Input data (plain text data or encrypted text data) is latched by a clock CLK1 and its output is initial-inverted, after which it is output from a selector (62). The least significant bit of the output data from the selector (62) is enlarge-inverted, after which it is XOR-ed with key data K1 and latched by a clock CLK2. The 48-bit data after the latch is divided by eight into 6 bits, which is replaced by 4-bit data, synthesized, and inverted. In the arithmetic operation of the second stage and after, data reshuffle-synthesized by a reshuffle-synthesizing circuit (66) is latched by the clock CLK1 and output from the selector (62). After the arithmetic operation of the 16-th stage, the data reshuffled by a reshuffle circuit (67) is contra-inverted. Thus, it is possible to realize an encryption/decryption arithmetic device.

The present invention provides a CRC (Cyclic Redundancy Check) checking circuit applicable to 64-bit bus bit width and a checking method, and can achieve a purpose of reducing the number of CRC-16 checkers only by means of 16-bit and 64-bit parallel CRC checkers plus an equivalent logic structure of delay determination and bitwise negation for transaction packet data in 16-bit, 32-bit, 48-bit and 64-bit alignment formats. The CRC-16 checking circuit provided by the present invention not only can implement checking of transaction packets in different sizes and different formats, but also is obviously improved in terms of area, power consumption and speed.