Special-purpose double production line RISC instruction system and its operation method

Abstract

The invention discloses a special double-pipeline RISC instruction system. The system is provided with two pipelines which are parallel mutually, and sequentially includes an instruction fetching unit, an instruction decoding unit, an instruction execution unit, a memory accessing unit and a data writing back unit. The system uses a double pipeline RISC instruction which comprises two incorporate single pipeline instructions. The invention further provides an operation method of the special double-pipeline RISC instruction system. The method includes the following steps: two parallel pipelines are arranged, namely, the instruction fetching unit, the instruction decoding unit, the instruction execution unit, the memory accessing unit and the data writing back unit are sequentially arranged; the double pipeline RISC instruction provided with two incorporate single pipeline instructions is arranged. Using the invention, the resource waste is avoided, wherein the resource waste is caused because a plurality of resources are not used during implementing algorithms when using a general digital signal processor. In addition, the invention has the advantages that the calculation more than 24 bits (48 bits inside) is realized, at the same time, the cost is low, and the power consumption is low.

Description

technical field [0001] The invention relates to an instruction system and an operation method, in particular to a special double-pipeline RIST instruction system and an operation method thereof. Background technique [0002] Computer instructions are generally composed of operation codes and address codes. Different instruction systems have differences in the structure of instructions: first, whether the number of digits in the instruction word length is fixed or variable; second, whether the number of digits in the operation code is quantitative or Floating quantity; there is also the structure and addressing mode of the address. These different factors make computer instructions divided into "simple instructions" and "complex instructions". The difference in the form of instructions also causes the difference in the internal structure of the CPU. At present, the instruction system of the CPU can be divided into two systems: CISC (Complex Instructor Set Computing, complex...

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Problems solved by technology

[0004] However, in the traditional RSIC structure, a single pipeline structure is usually adopted, and only one instruction can be executed within one system clock cycle, and the operation speed and efficiency are limited.

In addition, when the function and performance of the integrated circuit chip are enhanced, if each data processing module is directly mapped to the corresponding circuit by using the method of directly mapping the algorithm to the hardware, the required hardware area will increase with the increase in the number of computing units or the number of signal processing bits. a substantial increase in the number of

And the method of directly mapping the algorithm to the hardware has poor compatibility. Once the function or algorithm is changed, it is necessary to add circuit modules or modify the circuit structure.

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