Arithmetic device and encryption/decryption device

Abstract

Input data (plain text data or encrypted text data) is latched by a clock CLK1 and its output is initial-inverted, after which it is output from a selector (62). The least significant bit of the output data from the selector (62) is enlarge-inverted, after which it is XOR-ed with key data K1 and latched by a clock CLK2. The 48-bit data after the latch is divided by eight into 6 bits, which is replaced by 4-bit data, synthesized, and inverted. In the arithmetic operation of the second stage and after, data reshuffle-synthesized by a reshuffle-synthesizing circuit (66) is latched by the clock CLK1 and output from the selector (62). After the arithmetic operation of the 16-th stage, the data reshuffled by a reshuffle circuit (67) is contra-inverted. Thus, it is possible to realize an encryption / decryption arithmetic device.

Description

technical field [0001] The present invention relates to a data computing device and a data encryptor / decryptor for data computing to encrypt and / or decrypt data. Background technique [0002] Figure 5 The shown device is designed as an encryptor / decryptor conforming to the DES (Data Encryption Standard) encryption algorithm. [0003] Key data (secret key) and input data (plain text data or encrypted text data) each consist of 64 bits, and are latched in latch circuits 81 and 82 respectively according to clock CLK. Also, a mode signal indicating encryption or decryption is latched in the latch circuit 83 according to the clock CLK. [0004] The key data output from the latch circuit 81 is supplied to the key generator 90, and 16 levels of key data K1-K16 each consisting of 48 bits are sequentially output from the key generator 90. [0005] More specifically, the 64-bit key data output from the latch circuit 81 is converted into 56-bit key data in the conversion circuit 91,...

AI Technical Summary

Problems solved by technology

[0012] However, in the encryption / decryption calculation device described above, the key generator 90 is an asynchronous circuit not including any latch circuit (sampling circuit), in which 16 levels of key data are generated from input key data every time, and only Selected by the selector 99 so that a lot of noise (variation in signal line potential) is superimposed on the key data K1-K16 output from the key generator 90 near the transition point, thereby increasing power consumption in the calculator 100

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