Reconfigurable integer-floating point multiplier

A floating-point, multiplier technology, applied in the fields of instrumentation, computing, electrical digital data processing, etc., can solve the problems of inability to take into account precision and resource consumption, single function of the multiplication unit, etc., to shorten the critical path and improve resource utilization. , good functional effect

Active Publication Date: 2021-07-23
XI AN JIAOTONG UNIV
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The purpose of the present invention is to overcome the shortcomings of the existing multiplication unit in the above-mentioned prior art that the function is single, and the accuracy and resource consumption cannot be taken into consideration, and a reconfigurable integer-floating point multiplier is provided.

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Embodiment Construction

[0033] In order to enable those skilled in the art to better understand the solutions of the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only It is an embodiment of a part of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts shall fall within the protection scope of the present invention.

[0034] It should be noted that the terms "first" and "second" in the description and claims of the present invention and the above drawings are used to distinguish similar objects, but not necessarily used to describe a specific sequence or sequence. It is to be understood that the data so used are interchangeable under appropriate ...

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Abstract

The invention belongs to the field of digital signal processing, and discloses a reconfigurable integer-floating point multiplier which comprises an enabling control module, an integer-floating point preprocessing module, a pre-operation module, a reconfigurable multiplication module and an order matching module. The enabling control module generates a first control signal and a second control signal; the integer-floating point preprocessing module obtains first floating point type data and second floating point type data to obtain a first expansion mantissa and a second expansion mantissa; the front operation module obtains a sign bit of the floating point result and a temporary order code of the floating point result; the reconfigurable multiplication module obtains a temporary mantissa of an integer result or a floating point result; the order matching module obtains the mantissa and the order code of the floating point result. According to the method, floating point multiplication operation can be achieved, integer multiplication operation can be achieved under the condition that extra resources are not increased, the requirements of a current artificial intelligence chip can be fully met, data operation modes can be flexibly selected when different requirements are met, and the method has the better resource utilization rate, functionality and universality.

Description

technical field [0001] The invention belongs to the field of digital signal processing and relates to a reconfigurable integer-floating point multiplier. Background technique [0002] In recent years, with the advent of the era of artificial intelligence, people have invested in the upsurge of research on intelligent products. Due to the huge advantages of convolutional neural networks in the fields of target detection, image processing, and speech recognition, convolutional neural networks It has also become a research hotspot in academia and industry. Its advantage lies in connecting local relationships and obtaining a network structure of weight sharing. [0003] Convolutional neural network training mainly uses CPU and GPU, and its weights and biases are all floating-point numbers. With the development of VLSI, based on the advantages of speed and integration, more and more network structures after training are selected in FPGA or ASIC platform implementation, due to th...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F7/487G06F7/485
CPCG06F7/4876G06F7/485
Inventor 张斌王凯桂小琰张玉龙张泽
Owner XI AN JIAOTONG UNIV
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