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This application relates to a stacked interlocking semiconductor packaging structure, comprising: a substrate, a base plate, two chips, a packaging layer, and a protective shell; the substrate is disposed on the top surface of the base plate, and two chips are disposed on the substrate, with the packaging layer encapsulating the chips and the substrate; the protective shell is disposed on the top surface of the base plate and surrounds the sidewalls of the packaging layer; the protective shell includes: two or more stacked rings, each ring having a limiting groove on its inner sidewall, and the packaging layer having multiple limiting protrusions on its sidewalls, the limiting protrusions matching the limiting grooves for embedding within the limiting grooves. The protective shell surrounding the packaging layer effectively isolates and protects the packaging layer, preventing damage caused by direct exposure of the packaging layer's sidewalls to the outside. This application utilizes a stacked, interlocking ring structure to reliably complete the packaging process of microelectronic components or semiconductor devices; the overall structure is simple and easy to manufacture; it has significant advantages in terms of process speed and cost.