Carry verification device of floating point unit for multiply and summation, and multiplication CSA compression tree

A calibration device and floating-point multiplication technology, which is applied in the direction of instruments, electrical digital data processing, digital data processing components, etc., can solve problems such as data calculation errors
CN101093442AActive Publication Date: 2007-12-26LOONGSON TECH CORP
0 Cites 12 Cited by

Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
LOONGSON TECH CORP
Publication Date
2007-12-26

Smart Images

  • Figure 1
    Figure 1
  • Figure 2
    Figure 2
  • Figure 3
    Figure 3
Patent Text Reader

Abstract

A floating point multiplier-adder is prepared for using carry-over judgment unit to judge whether added result is carried-over or not by utilizing data of compression carry-over unit and compression sum unit as input value, outputting carry-over calibration bit M according to carry-over state, using carry-over calibration unit to operate high 55 bit and highest bit for making carry-over correction and outputting two sets of 55 bit values into high 55 bit in two set of data on 161 bit adder.
Need to check novelty before this filing date? Find Prior Art

Description

technical field

[0001] The present invention relates to the technical field of microprocessors, in particular to a floating-point multiplication-add component design technology in a microprocessor, in particular to a floating-point multiplication-adder and its multiplication carry-save adder (CSA) compression tree Carry check device. Background technique

[0002] In order to achieve high efficiency of floating-point calculations, both floating-point multiplication and addition in the microprocessor are implemented using a floating-point arithmetic unit—a floating-point multiply-adder (Floating-point Multiply-Add Fused Unit, FMAF). The instruction execution of the floating-point multiply-accumulator (FMAF) requires 3 operands A, B, and C to perform (A×B)+C operations. When the operand C in the multiply-add instruction is set to 0, the multiplication instruction is executed. , when the operand B is set to 1, the addition instruction is executed.

[0003] The operand of the f...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More