Carry verification device of floating point unit for multiply and summation, and multiplication CSA compression tree

A calibration device and floating-point multiplication technology, which is applied in the direction of instruments, electrical digital data processing, digital data processing components, etc., can solve problems such as data calculation errors

Active Publication Date: 2007-12-26
LOONGSON TECH CORP
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Problems solved by technology

Since the multiplication only takes 106 bits, this error is masked in the multiplier, and if no processing is done in the multiplier, it will cause calculation errors for some data due to wrong carry

Method used

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  • Carry verification device of floating point unit for multiply and summation, and multiplication CSA compression tree
  • Carry verification device of floating point unit for multiply and summation, and multiplication CSA compression tree
  • Carry verification device of floating point unit for multiply and summation, and multiplication CSA compression tree

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Embodiment Construction

[0043] In order to make the purpose, technical scheme and advantages of the present invention clearer, below in conjunction with accompanying drawing and embodiment, a kind of floating-point multiplication adder of the present invention and its multiplication Carry Save Adder (CSA) compression tree carry checking device For further details. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

[0044] In order to achieve the purpose of the present invention, as shown in Figure 1, the floating-point multiplier-adder of the present invention comprises negotiator 6, bit alignment shifter 7, the first multiplication carry save adder (CSA) 1, the second 3: 2 Carry-Saving Adder (CSA) 2, 161-bit Adder 5, Normalization and Rounding Unit 8, and Multiplicative Carry-Saving Adder (CSA) Compression in Parallel to Second 3:2 Carry-Saving Adder (CSA) 2 Carry checker for trees.

[0045] The ...

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Abstract

A floating point multiplier-adder is prepared for using carry-over judgment unit to judge whether added result is carried-over or not by utilizing data of compression carry-over unit and compression sum unit as input value, outputting carry-over calibration bit M according to carry-over state, using carry-over calibration unit to operate high 55 bit and highest bit for making carry-over correction and outputting two sets of 55 bit values into high 55 bit in two set of data on 161 bit adder.

Description

technical field [0001] The present invention relates to the technical field of microprocessors, in particular to a floating-point multiplication-add component design technology in a microprocessor, in particular to a floating-point multiplication-adder and its multiplication carry-save adder (CSA) compression tree Carry check device. Background technique [0002] In order to achieve high efficiency of floating-point calculations, both floating-point multiplication and addition in the microprocessor are implemented using a floating-point arithmetic unit—a floating-point multiply-adder (Floating-point Multiply-Add Fused Unit, FMAF). The instruction execution of the floating-point multiply-accumulator (FMAF) requires 3 operands A, B, and C to perform (A×B)+C operations. When the operand C in the multiply-add instruction is set to 0, the multiplication instruction is executed. , when the operand B is set to 1, the addition instruction is executed. [0003] The operand of the f...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F7/57
Inventor 齐子初胡伟武
Owner LOONGSON TECH CORP
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