64-bit fixed and floating point multiplier unit supporting complex operation and subword parallelism

A complex number operation and complex number multiplication technology, applied in the field of 64-bit fixed-floating point multipliers, can solve the problems of increasing chip area and power consumption, rapid expansion of multiplier computing resources, and reducing performance, so as to reduce key path delays, The effect of reducing computing resource overhead

Active Publication Date: 2010-09-22
BEIJING SMART LOGIC TECH CO LTD
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AI Technical Summary

Problems solved by technology

[0006] Subword parallelism and complex multiplication can improve multiplier performance, however, this requires additional configuration components in the critical path of the multiplier, which increases data path latency and degrades performance
In addition, due to the support for different data lengths and operations, the multiplier operation resources will be expanded rapidly, thereby increasing the chip area and power consumption

Method used

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  • 64-bit fixed and floating point multiplier unit supporting complex operation and subword parallelism
  • 64-bit fixed and floating point multiplier unit supporting complex operation and subword parallelism
  • 64-bit fixed and floating point multiplier unit supporting complex operation and subword parallelism

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Embodiment Construction

[0034] In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be described in further detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0035] The 64-bit fixed-floating-point multiplier provided by the present invention is a fixed-floating-point multiplier that supports subword parallel and complex operations. The multiplier supports 8, 16, 32, and 64 fixed-point multiplication operations, and supports simplified IEEE754 standard Single / double-precision floating-point operations, and supports 32, 64-bit complex multiplication.

[0036] Firstly, the realization principle of the present invention is introduced below, which mainly includes subword integration scheme, optimized subword integration structure and complex multiplication operation.

[0037] 1), subword integration scheme

[0038] Subword integration refers to combining multipliers with smaller b...

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Abstract

The invention discloses a 64-bit fixed and floating point multiplier unit supporting complex operation and subword parallelism. The multiplier unit is formed by combining four 32-bit multiplier units, wherein each 32-bit multiplier unit contains a 'carry' string used as output and an 'And' string used as output; the four 32-bit multiplier units contain four 'carry' strings and four 'And' strings; and the four 'carry' strings and the four 'And' strings are compressed by a 8-2 compressor to obtain a new 'carry' string and a new 'And' string for summation, so that the sum is used as the output of the multiplier unit. The 64-bit fixed and floating point multiplier unit reduces the time delay of key paths and the expense of operation resources.

Description

technical field [0001] The invention relates to the technical field of high-performance digital signal processors, in particular to a 64-bit fixed-floating point multiplier supporting complex operations and subword parallelism (Single Instruction Multiple Data, SIMD). Background technique [0002] In digital signal processing algorithms (such as FFT, FIR filtering, matrix-vector dot product, etc.), multiplication operations occupy a large proportion. Therefore, optimizing the algorithm and structure of the multiplier becomes the key to improving the performance of the processor. [0003] Different digital signal processing fields have different requirements for multiplication operations. In the field of communication processing, 8-bit or 16-bit fixed-point data is mostly used; in the field of image and radar signal processing, single-precision floating-point or even double-precision floating-point data is mostly used. . At the same time, a large number of digital signal pr...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F7/57
Inventor 王东琳张志伟尹志刚林啸谢少林闫寒薛晓军
Owner BEIJING SMART LOGIC TECH CO LTD
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