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Reconfigurable universal fixed floating-point multiplier

A technology of fixed-point multiplier and multiplier, which is applied in the direction of instruments, electrical digital data processing, digital data processing components, etc., can solve problems such as single fixed-point multiplication or floating-point multiplication, achieve good versatility, and reduce computing resources Overhead, the effect of improving the efficiency of multiplication operations

Active Publication Date: 2017-07-14
NANJING UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the existing multipliers generally only support a single fixed-point multiplication or floating-point multiplication

Method used

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  • Reconfigurable universal fixed floating-point multiplier
  • Reconfigurable universal fixed floating-point multiplier
  • Reconfigurable universal fixed floating-point multiplier

Examples

Experimental program
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Embodiment Construction

[0035] The solution of the present invention will be described in detail below in conjunction with the accompanying drawings.

[0036] Such as figure 1 As shown, the fixed-floating-point universal multiplier of this embodiment is composed of a 24-bit fixed-point multiplier, a gating circuit, a truncation / exponent bit carry, a selector, a sign bit judgment, and an 8-bit adder. The configuration signal and data are input from the outside, and the data operation path is determined by the configuration signal (select 24-bit fixed-point multiplication operation or single-precision floating-point operation).

[0037] The truncation / exponent bit carry module mainly determines the mantissa bit and exponent bit carry of the single-precision floating-point product. The mantissa bits of single-precision floating point are 23 bits in total, the equivalent mantissa bits are 24 bits, and the highest bit is 1. Then, the highest two digits of the 48-bit fixed-point number obtained by perfor...

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PUM

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Abstract

The invention provides a universal fixed floating-point multiplier, which can realize not only 24-bit fixed-point multiplication operation but also 32-bit single-precision floating-point multiplication operation. According to the multiplier, a fixed-point multiplier is separated from a main body structure, and the 24-bit fixed-point multiplier is reconfigured as a single-precision floating-point multiplier. The 24-bit fixed-point multiplier consists of four 12-bit multipliers, wherein each 12-bit multiplier adopts a BOOTH algorithm, and operation is finished through a contracted structure of multiplication accumulation, so that the multiplication operation efficiency is effectively improved and the operation resource overhead is reduced. The multiplier except the 24-bit fixed-point multiplier does not additionally occupy excessive resources, so that the universality of the multiplier is effectively improved under the condition of ensuring operation precision and data throughput.

Description

technical field [0001] The invention belongs to the technical field of digital signal processing, in particular to a reconfigurable fixed-floating point universal multiplier. Background technique [0002] In the design of high-performance microprocessors and DSP chips, the multiplier is a key component. Therefore, optimizing the multiplier plays a vital role in improving the overall processor performance. [0003] Different digital signal processing fields have different requirements for multiplication operations. According to the data types used in operations, multipliers can be divided into fixed-point multipliers and floating-point multipliers. The fixed-point multiplier requires less computing resources, but has lower precision; the floating-point multiplier requires more computing resources, but has high precision. They each have advantages and disadvantages for their application. However, the existing multipliers generally only support a single fixed-point multiplic...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F7/523
CPCG06F7/5235
Inventor 潘红兵朱杏伟李丽王晨曦王宇宣秦子迪陈金锐李伟何书专
Owner NANJING UNIV
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