Mode-based multiply-add processor for denormal operands

Abstract

In a denormal support mode, the normalization circuit of a floating-point adder is used to normalize or denormalized the output of a floating-point multiplier. Each floating-point multiply instruction is speculatively converted to a multiply-add instruction, with the addend forced to zero. This preserves the value of the product, while normalizing or denormalizing the product using the floating-point adder's normalization circuit. When the operands to the multiply operation are available, they are inspected. If the operands will not generate an unnormal intermediate product or a denormal final product, the add operation is suppressed, such as by operand-forwarding. Additionally, each non-fused floating-point multiply-add instruction is replaced with a multiply-add instruction having a zero addend, and a floating-point add instruction having the addend of the original multiply-add instruction is inserted into the instruction stream. Upon inspection of the operands, if an unnormal intermediate result or a denormal final result will not occur, the addend may be restored to the multiply-add instruction and the add instruction converted to a NOP.

Description

technical field [0001] The present disclosure relates generally to the field of processors and more particularly to a pattern-based method of recoding floating point multiply instructions as floating point multiply-add instructions to compute denormalized operands. Background technique [0002] Microprocessors perform computational operations on numerical values ​​in a wide variety of applications. High execution speed, low power consumption, and small size are important goals for processor designers, especially in embedded applications such as portable electronic devices. Modern processors employ a pipelined architecture in which sequential instructions, each with multiple execution steps, overlap when executed. In a pipelined architecture, each instruction is executed in a series of execution stages, such as fetch, decode, execute, and writeback, each of which may include multiple pipeline stages. The pipeline stage consists of storage elements and logic that executes al...

AI Technical Summary

Problems solved by technology

However, such additional circuitry increases silicon area, increases delay and creates feedthrough lag, thus potentially increasing minimum cycle time and thus reducing maximum operating frequency

Also, denormal numbers are rarely encountered, and optimizing performance for said rare cases at the expense of common cases reduces total processor performance

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