Serial communication protocol controller, byte splitting circuit and 8b10b encoder

A serial communication protocol and byte splitting technology, which is applied in the field of microelectronics, can solve the problems that the maximum operating frequency of the circuit is difficult to reach 500MHz, increase the chip area and power consumption, and complicate the coding logic relationship. The effects of integration, area saving, and dynamic power improvement
CN104467865BActive Publication Date: 2018-08-03SHANDONG SINOCHIP SEMICON
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
SHANDONG SINOCHIP SEMICON
Publication Date
2018-08-03

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Abstract

The invention discloses a serial communication protocol controller, which includes a byte splitting circuit and an 8b10b encoder. The byte splitting circuit receives bus data, transmits it to the 8b10b encoder, and completes bus data and 8b / 10b encoding The matching of data with different clock frequencies and different bit widths between devices. The byte splitting circuit includes FIFO, controller and register, and the byte splitting circuit extracts 32-bit bus data byte 0, byte 1, byte 2, byte 3 to form source data word 1; byte 4, byte 5. Byte 6 and byte 7 form the source data word 2, obtain 4 beats of 8-bit output data, then write them into FIFO in turn, and then read them into the register under the action of the controller, and at the same time follow the byte from low to high The sequence is transmitted sequentially to the encoder input. The invention also provides a byte splitting circuit and an 8b10b encoder adopted by the serial communication protocol controller. The invention effectively solves the matching problem of the data bandwidth of the sending end of the high-speed serial communication protocol.
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Description

technical field

[0001] The present invention relates to the technical field of microelectronics, in particular to a high-speed serial communication protocol controller circuit, in particular to a byte splitting circuit and an 8b10b encoder. Background technique

[0002] In the traditional parallel data transmission mode, the data transmission mode generally adopts a special data bus and a clock line for synchronous transmission. The bandwidth limitation of the traditional parallel bus can no longer meet the astonishing demands of the development of the hardware subsystem speed and the increasing data throughput, which is mainly manifested in the following two aspects: As the bus frequency rises, it will affect the connection to the bus at the same frequency. Therefore, even if the bus clock frequency is increased, the bus bandwidth cannot be significantly improved; although the bandwidth can be increased by increasing the number of parallel channels, the synchronous transmis...

Claims

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