Time synchronization method and clock device

Abstract

The invention provides a time synchronization method and a clock device, the limitation of a block port on a precision time protocol (PTP) synchronization message is cancelled, a local clock is amended according to the PTP synchronization message transmitted from an optimal path, as the hop count of routing of the PTP synchronization message is minimal, the cumulative error is also minimal and the time synchronization precision is further improved. Furthermore, when the PTP synchronization message is received through a slave port and the clock device has a master port, after clock information carried in the PTP message is amended, the master port is used for forwarding the PTP synchronization message so as to enable the follow-up clock device to conveniently perform precision time synchronization.

Description

technical field [0001] The invention relates to the technical field of network communication, in particular to a time synchronization method and a clock device. Background technique [0002] The IEEE1588 protocol is a relatively accurate clock synchronization solution in Ethernet, and its basic function is to keep other clocks in the distributed network synchronized with the most accurate clock. A precision time protocol (PTP, Precision Time Protocol) is defined in the IEEE1588 protocol, which is used to accurately synchronize the clocks of network nodes in standard Ethernet or other distributed bus systems using multicast technology, and its precision can reach nanometers. second level. [0003] In the network, the clock priority is usually set for each clock device, and each clock device sends an Announce message carrying its own clock priority in the network to elect the clock device with the highest clock priority, which has the highest clock priority The clock device ...

AI Technical Summary

Problems solved by technology

For C3, the time synchronization path is from C2 to C1, and then from C1 to C3, which requires two time corrections. For the better path C2 to C3, it cannot be used due to the limitation of blocking port P1.

As the number of node hops on the time synchronization path increases, the error will accumulate and the accuracy will decrease accordingly. Obviously, the clock synchronization method in the prior art cannot obtain the final accuracy.

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