10-gigabit Ethernet TCP offload engine (TOE) system realized based on FPGA

Abstract

The invention discloses a 10-gigabit Ethernet TCP offload engine (TOE) system realized based on an FPGA, comprising the FPGA for realizing a TCP / IP protocol stack and a 10-gigabit Ethernet MAC layer, a 10-gigabit Ethernet PHY chip connected with the FPGA, a 10G optical transceiver module connected with the FPGA and used for serving as a 10-gigabit Ethernet transmission medium, and a DDR external memory connected with the FPGA and used for data caching. The FPGA is creatively adopted to realize the TCP / IP protocol stack, replacing a soft TCP / IP protocol stack realized by a conventional way of using a processor and an operation system with a hardware manner. According to the system, the processing speed of the TCP / IP protocol stack is effectively increased, the smoothness and balance of 10-gigabit Ethernet transmission are realized, and most importantly, computer application and network protocol separation is realized.

Description

technical field [0001] The invention relates to the field of the high-performance TCP / IP protocol stack of the 10-Gigabit network, in particular to a system of the TCP protocol unloading engine TOE of the 10-Gigabit network realized based on FPGA. Background technique [0002] With the rapid development of network technology, especially optical fiber technology, high-speed communication networks such as optical fiber communication networks are rapidly becoming the main means of network transmission, and network bandwidth is also constantly improving. The performance requirements of network applications are characterized by high throughput, low latency, high bandwidth, low host overhead, and low storage overhead. According to Thumb's law, about 1 Hertz of CPU performance is required to transmit 1 bit of data. Therefore, with the emergence of Gigabit Ethernet and 10 Gigabit Ethernet, the consumption of CPU resources is increasing. In addition, since most operating systems are...

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Problems solved by technology

[0005] There are also relevant reports at home and abroad on the use of FPGA as the main implementation of TOE technology, mainly focusing on two aspects: one is the implementation of the TCP / UDP protocol for 100M or 1000M network, but this implementation cannot meet the requirements of 10G transmission in terms of speed. requirements, and only one or two network connections can be realized, so it is greatly limited in high-speed applications; the other is to realize a single 10 Gigabit connection on the MAC layer, but this connection needs to rely on the promiscuous mode support of the receiver's network card , not only the maximum speed is limited, but also the versatility is poor

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