The invention belongs to the field of computer
system construction, and particularly relates to a CPU
bottleneck analysis model based on a performance counter. The technical problems that in a method for discovering the performance
bottleneck of the CPU by building a CPI stack in the prior art, average
delay evaluation of failure events needed by performance evaluation is limited, failure
delay is difficult to fully
expose due to the streamline technology of a modern processor, and therefore discovering of the performance
bottleneck of the CPU by the CPI stack is affected are solved. According to the method, each
clock cycle pause of a
program instruction is allocated to a corresponding failure event, and a relationship between the instruction pause and the failure event is obtained by extracting a key performance
signal in a program execution process based on an interactive analogy model, so that a
performance model is constructed and is used for guiding
program optimization and processor hardware iteration. The CPIstack
algorithm constructed by using the performance counter can be deployed on a prototype
verification platform, and the performance of the processor can be accurately evaluated.