FPGA-based design method for improving the speed of BCPNN

A design method and speed technology, applied in the field of artificial intelligence, can solve problems such as high computational complexity, achieve the effects of reducing resource consumption, increasing weight and bias update speed, and improving computing speed

Pending Publication Date: 2020-11-03
FUDAN UNIV +1
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Problems solved by technology

However, although this scheme simplifies the calculation process, the computational complexity is still high

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  • FPGA-based design method for improving the speed of BCPNN
  • FPGA-based design method for improving the speed of BCPNN
  • FPGA-based design method for improving the speed of BCPNN

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Embodiment Construction

[0024] It should be clear that the described embodiments are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.

[0025] The present invention uses the method of modular design, and the goal is to accelerate the update process of the state variable, weight and bias of the Bayesian belief propagation neural network on the FPGA hardware, so as to obtain the purpose of improving the weight and bias update speed of the neural network . Among them, FPGA (Field Programmable Gate Array) is a product further developed on the basis of programmable devices such as PAL and GAL. It emerged as a semi-custom circuit in the field of application-specific integrated circuits (ASIC), which not only solves the shortcomings of custom circuits, but also overcomes the shortc...

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Abstract

The invention discloses an FPGA-based design method for improving the speed of a BCPNN, and relates to the technical field of artificial intelligence, and the method comprises the steps: updating variables, weights and offsets of synaptic states in the BCPNN on hardware through modular design; and achieving exponential operation on the FPGA through the lookup table. through a parallel algorithm, the speed of the weight and bias updating process of the synaptic state in the BCPNN is increased; through module multiplexing of the adder and the multiplier, the resource overhead is reduced under the condition of keeping the same computing performance. The method provided by the invention not only has higher calculation performance, but also has higher calculation accuracy, and can effectively improve the weight and offset updating speed of the BCPNN.

Description

technical field [0001] The invention relates to the technical field of artificial intelligence, in particular to an FPGA-based design method for increasing the speed of BCPNN. Background technique [0002] Bayesian Belief Propagation Neural Networks (BCPNNs) provide a flexible but computationally complex mechanism for synaptic plasticity. BCPNN learning rules, built on Bayesian statistics and clearly linked to biological plasticity processes, have been applied in many fields, from data classification, associative memory, reward-based learning, probabilistic inference to cortical attractor memory networks. [0003] In the spike-based version of this learning rule, presynaptic, postsynaptic, and intersynaptic co-activity is tracked in three stages of low-pass filtering, requiring a total of eight state variables whose dynamics are typically obtained using The Euler method with a fixed step size is used for simulation. The research group at TU Dresden derived an analytical so...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06N3/063G06N3/04
CPCG06N3/063G06N3/047G06N3/045
Inventor 王德裕梁龙飞刘力政邹卓环宇翔郑立荣
Owner FUDAN UNIV
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