Multi-party central processing unit communication architecture based on field-programmable gate array control

A central processing unit and gate array technology, applied in electrical digital data processing, instruments, etc., can solve the problems of high software programming pressure, long time, single transmission mode, etc.

Inactive Publication Date: 2020-05-22
PEKING UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0011] The advantage of using the serial port master-slave mode for communication is that it has less dependence on software programs. The disadvantage is that it has a certain dependence on th

Method used

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  • Multi-party central processing unit communication architecture based on field-programmable gate array control
  • Multi-party central processing unit communication architecture based on field-programmable gate array control
  • Multi-party central processing unit communication architecture based on field-programmable gate array control

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Experimental program
Comparison scheme
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Embodiment Construction

[0020] Communication Architecture: figure 1

[0021] FPGA internal logic module: figure 2

[0022] Communication method:

[0023] 1. Communication between CPUs is controlled by FPGA.

[0024] 2. The CPU and the FPGA communicate through a high-speed transceiver port and an interrupt signal IO.

[0025] 3. The CPU can send various types of packets to the FPGA through the high-speed transceiver port at any time, and the FPGA side processes the received packets immediately.

[0026] 4. In addition to the return packet required by the CPU, when the FPGA actively wants to send a packet to the CPU, it should first use the interrupt port to apply to the CPU side. The waveforms of interrupt request signal and response signal are as follows: image 3 shown. The FPGA then sends the packet to the CPU according to the required information carried in the packet responded by the CPU.

[0027] 5. There are only two cases where the FPGA actively sends packets to the CPU: 1) CPU status...

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Abstract

The invention provides a multi-party central processing unit communication architecture based on field-programmable gate array control, which is characterized in that data forwarding communication iscarried out among a plurality of CPU chips through the control of FPGA chips, and the FPGA chips are used for scheduling data streams of all parties. When the CPU _ A needs to send data to the CPU _ B, the data packet is firstly sent to the FPGA chip in a special format; the FPGA analyzes and caches the data packet and notifies the CPU _ B to prepare to receive data in an interrupt mode, and afterthe CPU _ B reads the data from a buffer area of the FPGA, communication between CPUs is completed once. The FPGA chip receives an instruction issued by the CPU chip at any time through the high-speed data transceiving port, and when the FPGA chip actively needs to communicate with the CPU chip, an interrupt request is sent to the CPU chip through the interrupt signal IO pin.

Description

technical field [0001] The present invention relates to the application technical field of communication between a central processing unit (Central Processing Unit, CPU) and a field programmable gate array (Field-Programmable Gate Array, FPGA), and specifically relates to a The CPU chips perform data forwarding and communication through the control of the FPGA chip, and the FPGA chip schedules the data flow of all parties. Background technique [0002] In order to meet high-end applications such as communication, multimedia and digital processing, the SoC not only integrates one processor, but also integrates multiple processors into the system, and even needs to work together with off-chip processors. Since the system integrates multiple processors, each processor is equivalent to a host of the system. When each processor communicates with shared resources, there are certain logical conflicts, which cause a series of problems in the internal communication of the system. At...

Claims

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Application Information

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IPC IPC(8): G06F13/16G06F13/24
CPCG06F13/1673G06F13/1694G06F13/24
Inventor 严伟章少云
Owner PEKING UNIV
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