Static zero-consumption power-on resetting circuit

Abstract

The invention discloses a static zero-consumption power-on reset circuit which comprises a voltage detecting circuit, an impulse latch circuit, an output buffer circuit, and a zero clearing reset circuit. Wherein one input end of the voltage detecting circuit is connected to a power supply, the other end thereof is connected to an enable control output end of the output buffer circuit; an output end of the voltage detecting circuit is connected to an input end of the impulse latch circuit; an output end of the impulse latch circuit is connected to an input end of the output buffer circuit; an enable control output end of the voltage detecting circuit and an input end of the zero clearing reset circuit are respectively connected with an output end of the output buffer circuit; and an input end of zero clearing reset circuit receives an external zero clearing reset signal, and an output end thereof outputs an electrifying reset signal. The invention has a simple and novel structure, needs no external RC element, the occupied area of a chip is small, static consumption is nearly zero, and the invention can be applied to the SoC chip with low consumption.

Description

technical field [0001] The invention belongs to the field of integrated power management circuits, in particular to a CMOS static zero-power-consumption power-on reset circuit, which is especially suitable for application in low-power SoC chips. Background technique [0002] Power-On Reset (POR, Power-On Reset) circuits have been widely integrated into SoC chips. In the early stage of power-on of a circuit system, the power supply voltage has not yet reached the expected stable state, and the circuit node voltage and logic state are unstable, which may cause system error operation. In order to make the system work from a predetermined initial state, it is necessary to use the power-on reset circuit to generate a POR signal at the initial stage of power-on to initialize the system. [0003] figure 1 (a) discloses an existing power-on reset circuit, which includes a PMOS transistor M1 and a capacitor C1. The source of the PMOS transistor M1 is connected to the external powe...

AI Technical Summary

Problems solved by technology

[0007] First, in order to make the comparator CMP1 work normally, it is necessary to add an additional reference source generation circuit to provide the reference voltage Vref, which increases the complexity of the circuit design

[0008] Second, the above-mentioned circuit still needs to consume current when it is static, which increases the power consumption of the circuit system to a certain extent, especially when the circuit system is in a standby or dormant state, this part of the power consumption will be quite prominent

[0009] therefore, figure 2 The power-on reset circuit disclosed in is not only too complex in structure, but also consumes unnecessary current in static state, which reduces the system efficiency

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