A system and method for providing a software trap and patch function to low power, cost conscious, and space constrained applications. When a programming error in a first memory is discovered, a data structure comprising a trap address, patch code, and patch address are stored in a second memory. A power-on-reset process detects the presence of the data structure, and in response thereto, enables the trap and patch function. In operation, upon the occurrence of a trap condition, the first memory is disconnected from the data bus and a predetermined instruction circuit is activated. Upon activation thereof, the predetermined instruction circuit, which comprises solely combinational circuitry, places the op code of the predetermined instruction on the data bus. In one embodiment, in which the predetermined instruction is a software interrupt instruction, a predetermined bit of the PSR is placed in a defined state responsive to the occurrence of a trap condition. Upon execution of the software interrupt instruction, the processor executes an interrupt request service routine. There, the predetermined bit of the PSR is examined to see if it is in the predefined state. If so, and the interrupt was caused by a trap condition in contrast to a software interrupt, the service routine causes the processor to execute the patch code in place of the error-containing code. If not, signifying a hardware interrupt, another service routine is executed.