Method and system for improving timestamp precision

Abstract

The invention discloses a method and system for improving timestamp precision, and relates to the field of time synchronization, and the method comprises the steps: sending a second pulse signal or a frame positioning identification signal outputted by an OTN business processing chip to an LVDS SERDES interface of an FPGA; obtaining the rising edge position of the frame positioning identification signal through an LVDS SERDES interface, generating a real-time time sampling indication signal at the same time, and taking the current real-time time as an initial timestamp T; generating a sampling error compensation value [delta]t1 based on a non-zero sampling value corresponding to the real-time time sampling indication signal; and obtaining the current oversampling state based on the statistical result, wherein different oversampling states correspond to different oversampling error compensation values [delta]t2, and the final timestamp is equal to the sum of the initial timestamp T, the sampling error compensation value [delta]t1 and the oversampling error compensation value [delta]t2. The method is easy to implement, and the requirement for the time sequence of the FPGA device is low.

Description

technical field [0001] The invention relates to the field of time synchronization, in particular to a method and a system for improving time stamp precision. Background technique [0002] Time stamp is one of the key elements of time synchronization. The 1588 protocol specifies the method and requirements for time stamping. For event packets, time stamping is required when receiving and sending, which is convenient for calculating line delay. The jitter of the line delay is large, which will affect the performance index of time synchronization. With the advent of the 5G (5th generation mobile networks, fifth generation mobile communication technology) communication era, 5G communication has put forward new requirements and challenges for time synchronization technology, and improving the accuracy of time stamps is the key to meeting the new needs. When maintaining real-time time or processing time stamps, a 125MHz clock is usually used to sample the pulse-per-second signal ...

AI Technical Summary

Problems solved by technology

[0003] Commonly used methods to improve timestamp accuracy include increasing sampling clock frequency and multi-phase sampling. For FPGA (Field-Programmable Gate Array, Field Programmable Gate Array), the clock frequency can usually be increased to about 250MHz-300MHz, and then continue There is not much room to increase the frequency of the sampling clock; for the method of multi-phase sampling, because the routing of the clock and data in the FPGA is not easy to control accurately, resulting in large errors, the actual implementation effect is not ideal

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