Two-level comparator

Abstract

The present invention relates to a two-level comparator circuit, belonging to the technical field of analog integrated circuits. The two-level comparator circuit comprises an input level and a latch level. The input level comprises a first N-channel metal oxide semiconductor (NMOS) transistor (MN1), a second NMOS transistor (MN2), a third NMOS transistor (MN3), a first p-channel metal oxide semiconductor (PMOS) transistor (MP1), a second PMOS transistor (MP2), a third PMOS transistor (MP3) and a fourth PMOS transistor (MP4). The latch level comprises a fourth NMOS transistor (MN4), a fifth NMOS transistor (MN5), a sixth NMOS transistor (MN6), a seventh NMOS transistor (MN7), an eighth NMOS transistor (MN8), a ninth NMOS transistor (MN9), a fifth PMOS transistor (MP5), a sixth PMOS transistor (MP6), a seventh PMOS transistor (MP7) and an eighth PMOS transistor (MP8). Due to reset of a node X+ and a node X- in a latch level circuit, circuit maladjustment and noise are lowered. A pair of cross-coupling transistors MP1 and MP2 is added in the input level circuit, so that the comparator has the characteristic of working at a high-speed. The two-level comparator is applicable to system circuits of high accuracy.

Description

technical field [0001] The invention belongs to the field of electronic technology, relates to an analog integrated circuit design technology, in particular to a high-speed comparator circuit with low noise and low offset. Background technique [0002] A comparator is a circuit that compares an analog voltage signal to a reference voltage. The traditional two-tailed comparator structure, such as figure 1 As shown, it consists of two stages, namely, the input stage and the latch stage, wherein the input stage is the first stage, and the latch stage is the second stage. The tail current of the input stage is controlled by the clock signal CLK, and the tail current of the latch stage is controlled by the inversion CLKB of the clock signal. When the clock signal CLK=GND, the comparator enters the reset phase (RESET). Transistors MP1 and MP2 pull up the output nodes DI+ and DI- of the first stage to the power supply voltage VDD, so that the transistors MN6 and MN7 are turned o...

AI Technical Summary

Problems solved by technology

This traditional comparator is simple in structure and very fast, but has the following disadvantages: 1. The timing of the clock signal CLK and the inversion CLKB of the clock signal must be very accurate; 2. Since node X is at CLK=GND It has not been reset, resulting in relatively large offset of the comparator; 3. When the comparator enters the comparison stage, because the transistor MP5 enters the linear region, the noise is relatively large

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