10 results about "Memory form" patented technology

The invention discloses a storage system supporting Cache and RAM double-form access and an access method thereof, and the system comprises a data storage array which is divided into a plurality of structured storage sub-blocks; the storage mode register is used for storing a configuration value, and the configuration value is used for dynamically configuring each storage sub-block to work in a Cache mode or an RAM mode, so that the data storage array works in a full Cache mode or a full RAM mode or a Cache and RAM coexistence mode; and the storage access control logic is used for arbitrating the storage access request, mapping the storage access request to the corresponding storage sub-block for read-write access according to the access address and the configuration value, activating the storage sub-block mapped by the storage access request, and inactivating the storage sub-block not mapped by the storage access request. According to the method, dynamic configuration is achieved, access of Cache and RAM forms is supported at the same time, part of or all memory banks can be configured to be Cache or RAM, the advantages of the two memory forms are utilized at the same time, parallel access of a plurality of memory sub-blocks is supported, use is flexible and efficient, and power consumption is reduced.

Embodiments of the present application disclose a memory forming method and a memory. The memory forming method comprises the following steps: providing a substrate, a transistor column array is formed on a surface of the substrate; forming a stack structure covering the transistor column array, the stack structure comprises a first support layer and a first sacrificial layer which are stacked in sequence in a direction away from the substrate; forming a capacitor hole array penetrating through the stack structure, a plurality of capacitor holes in the capacitor hole array are arranged one-to-one corresponding to a plurality of transistor columns, and the capacitor holes expose the transistor columns; forming a first electrode layer and a filling layer on inner walls of the capacitor holes in sequence; forming a first gap hole array penetrating through the first support layer, the first gap hole array comprises a plurality of first gap holes arranged in an array, and each first gap hole is located between four first electrode layers adjacent to each other; removing the first sacrificial layer through the first gap hole array to expose the first electrode layer; and forming a dielectric layer and a second electrode layer covering the first electrode layer in sequence to form a capacitor array.

The invention discloses an emotion accompanying interaction method and a related device, and relates to the technical field of man-machine interaction, the emotion accompanying interaction method comprises the following steps: obtaining role description information of a virtual role and current dialogue information input by a target user, retrieving target memory related to the current dialogue information from a memory storage unit, the target memory comprises emotional change information of the virtual character, and the changed emotional state in the emotional change information is aligned with the real emotional state of the target user, generating a dialogue reply prompt instruction according to the current dialogue information, the character description information and the target memory, and inputting the dialogue reply prompt instruction into a configured dialogue large model, dialogue reply information output by the model is obtained and serves as the dialogue reply information of the virtual character to the current dialogue information. The emotion change information of the virtual character is stored in a memory form, continuous memory of the emotion of the virtual character is realized, so that a dialogue reply with richer and more smooth emotion expression can be generated, and the sense of reality of the virtual character is improved.

The invention relates to a sensor comprising a depth pixel having a controllable storage area which successively includes a potential barrier, a memory region, a pinch-off area; a transfer grid opposite the barrier; an inverse transfer grid opposite the barrier and the photosensitive region; a pinch-off grid opposite the memory forming a coupling capacitor with the memory. A charge flow path above the photosensitive region includes a collection area separated from the photosensitive region by a channel; and an initialization grid opposite the channel. A circuit is configured to: sample a signal from the memory; disconnect the pinch-off area and the capacitor; clear the memory by activating the inverse transfer and initialization grids; and read an electrical potential from the capacitor. (See Figure 3A for the abstract.)

An accelerator module includes a plurality of memories and a controller. The controller includes a plurality of memory controllers, a plurality of processing units, and a managing circuit. The plurality of memory controllers and the plurality of memories form a plurality of memory sub-channels. The plurality of processing units perform computational operations on a plurality of data stored in or read from the plurality of memories. The managing circuit redistributes tasks performed by the plurality of processing units or changes connections between the plurality of memory controllers and the plurality of processing units in response to a first memory sub-channel and a first processing unit being in a heavy-workload state.

The invention belongs to the technical field of electronics, and relates to an all-flash array for realizing inter-disk resource sharing based on hardware consistency interconnection. The all-flash array comprises a plurality of solid state disks; each solid state disk exposes a part of onboard memory through a CXL protocol, and the exposed onboard memory forms a global consistency memory domain, so that communication based on a shared memory can be carried out between the solid state disks; a solid state disk in an idle state is called as a creditor, the creditor calculates computing resources which can be borrowed, and availability of the computing resources is declared by writing idle resource descriptors; and calling the solid state disk lacking computing resources as a debtor, scanning idle resource descriptors of all other solid state disks by the debtor, and selecting at least one creditor to perform resource recovery so as to realize inter-disk resource sharing. According to the method, idle resources are utilized in a peak clipping and valley filling manner in a mode of sharing resources among disks in the all-flash array, so that the resource utilization rate can be improved.

The present application relates to a memory and a method for forming the same, the method comprising: providing a substrate; forming, in the substrate, a drain doped layer, a channel doped layer and a source doped layer which are sequentially stacked from inside of the substrate to a surface of the substrate; forming a bit line below the channel doped layer and at least partially in the drain doped layer, and a first isolation structure penetrating the bit line, the bit line and the first isolation structure extending along a first direction; forming, in the substrate, third isolation structures on both sides of the bit line extending along the first direction; and forming, in the substrate, a word line structure in the channel doped layer and a second isolation structure penetrating the word line structure, the word line structure and the second isolation structure extending along a second direction. The memory formed by the above method has improved storage density.

The application discloses a kind of inter-core communication method, device, multi-core controller and computer readable storage medium.The method comprises: obtaining the data encoding information corresponding to target data, the data encoding information includes sending core mask and receiving core mask;The validity check is carried out to the data encoding information, and the validity check result is determined;When the validity check result is check pass, the authority check is carried out based on the sending core mask or the receiving core mask, and the authority check result is determined;When the authority check result is check pass, the target data is transmitted through the inter-core communication queue in target inter-core memory;The target inter-core memory is the inter-core memory related to the authority of the target data to the current core among the two inter-core memories formed between the current core and target core.The method can improve the security and efficiency of inter-core communication, and reduce the load of processor core with higher load.

The invention provides a method for forming a multi-valued memory, which comprises the following steps of: forming a charge storage region in a semiconductor substrate, and forming a floating diffusion region at the upper part of the charge storage region; an annular vertical transfer transistor is formed around the floating diffusion region, and the spatial distance between any point of a channel region of the annular vertical transfer transistor and a gate dielectric layer of the annular vertical transfer transistor is smaller than a preset threshold value, so that silicon in the channel region of the floating diffusion region is completely exhausted, and the gate control capability is improved.

A memory and a forming method thereof, the forming method comprising: providing a substrate; forming a first mask layer on a surface of the substrate, a plurality of strip-shaped patterns being formed in the first mask layer; forming a second mask layer on the first mask layer, a plurality of first patterns and a plurality of second patterns being formed in the second mask layer, the plurality of first patterns being arrayed and overlapping the strip-shaped patterns, the plurality of second patterns covering end portions of the strip-shaped patterns; and etching layer by layer to the substrate with the first mask layer and the second mask layer as masks, so as to transfer the strip-shaped patterns, the first patterns and the second patterns into the substrate, and form a plurality of discrete active regions arrayed and a split groove corresponding to the first patterns and the second patterns. The memory formed by the method has improved reliability.