25 results about "Memory form" patented technology

The invention discloses a storage system supporting Cache and RAM double-form access and an access method thereof, and the system comprises a data storage array which is divided into a plurality of structured storage sub-blocks; the storage mode register is used for storing a configuration value, and the configuration value is used for dynamically configuring each storage sub-block to work in a Cache mode or an RAM mode, so that the data storage array works in a full Cache mode or a full RAM mode or a Cache and RAM coexistence mode; and the storage access control logic is used for arbitrating the storage access request, mapping the storage access request to the corresponding storage sub-block for read-write access according to the access address and the configuration value, activating the storage sub-block mapped by the storage access request, and inactivating the storage sub-block not mapped by the storage access request. According to the method, dynamic configuration is achieved, access of Cache and RAM forms is supported at the same time, part of or all memory banks can be configured to be Cache or RAM, the advantages of the two memory forms are utilized at the same time, parallel access of a plurality of memory sub-blocks is supported, use is flexible and efficient, and power consumption is reduced.

The invention relates to a memory forming method and a memory. The method comprises the steps of providing a substrate; forming stacked structures arranged at intervals and a first dielectric layer filled between the stacked structures on the substrate of the storage area, wherein each stacked structure comprises a first conductive layer, a storage structure and a sacrificial layer located on the top surface of the storage structure; removing the sacrificial layers to form a plurality of first grooves which are recessed relative to the surface of the first dielectric layer; and filling an electrode material in the first groove to form a first electrode layer. After the first dielectric layer is formed, the first electrode layer is formed by removing the sacrificial layer and then backfilling the electrode material, so that a top electrode is prevented from being damaged in the process of etching the multi-layer material, and an oxidation reaction and a nitridation reaction on the first electrode layer in the process of forming the first dielectric layer are avoided; the uniformity and the electrical uniformity of the first electrode layer are effectively improved, and the stability and the reliability of the memory are improved.

Embodiments of the present application disclose a memory forming method and a memory. The memory forming method comprises the following steps: providing a substrate, a transistor column array is formed on a surface of the substrate; forming a stack structure covering the transistor column array, the stack structure comprises a first support layer and a first sacrificial layer which are stacked in sequence in a direction away from the substrate; forming a capacitor hole array penetrating through the stack structure, a plurality of capacitor holes in the capacitor hole array are arranged one-to-one corresponding to a plurality of transistor columns, and the capacitor holes expose the transistor columns; forming a first electrode layer and a filling layer on inner walls of the capacitor holes in sequence; forming a first gap hole array penetrating through the first support layer, the first gap hole array comprises a plurality of first gap holes arranged in an array, and each first gap hole is located between four first electrode layers adjacent to each other; removing the first sacrificial layer through the first gap hole array to expose the first electrode layer; and forming a dielectric layer and a second electrode layer covering the first electrode layer in sequence to form a capacitor array.

The present invention provides a method for generating a reconstructed image, applicable to an input image having a target object. The method comprises: an encoder converting the input image into a feature map having multiple feature vectors; executing a training process based on multiple training images of multiple reference objects to generate multiple feature prototypes associated with the training images and storing the feature prototypes in a memory; selecting a portion of the feature prototypes from the memory based on multiple similarities between the feature prototypes and the feature vectors; generating an approximate feature map based on the portion of the feature prototypes and multiple weights, wherein the weights each represent the similarity between the feature prototypes and the feature vectors; and a decoder converting the approximate feature map into a reconstructed image. The encoder, decoder, and memory form an autoencoder. A defect classifier implemented using the image reconstruction method of the present invention is resistant to noise in the training data set.

The present disclosure relates to a memory and a memory forming method. The memory forming method includes: providing an initial substrate; etching the initial substrate to form a plurality of capacitor holes and a plurality of recesses that are connected to the capacitor holes in a one-to-one corresponding manner and located below the capacitor holes; forming an isolation layer that connects adjacent ones of the recesses and fills up the recesses, and using the initial substrate remaining below the isolation layer as a substrate; and forming a capacitor in the capacitor hole.

System-in-packages (SiPs) having hybrid high bandwidth memory (HBM) devices, and associated systems and methods, are disclosed herein. In some embodiments, the SiP includes a base substrate, as well as a processing device and a hybrid high-bandwidth memory (HBM) device each carried by the base substrate. The processing device includes a processing unit and a first cache memory associated with a first level of a cache hierarchy. The hybrid HBM device is electrically coupled to the processing unit through a SiP bus in the base substrate. Further, the hybrid HBM device includes an interface die, one or more memory dies carried by the interface die, and a shared bus electrically coupled to the interface die and each of the memory dies. The hybrid HBM device also includes a second cache memory formed on the interface die that is associated with a second level of the cache hierarchy.

The invention discloses an emotion accompanying interaction method and a related device, and relates to the technical field of man-machine interaction, the emotion accompanying interaction method comprises the following steps: obtaining role description information of a virtual role and current dialogue information input by a target user, retrieving target memory related to the current dialogue information from a memory storage unit, the target memory comprises emotional change information of the virtual character, and the changed emotional state in the emotional change information is aligned with the real emotional state of the target user, generating a dialogue reply prompt instruction according to the current dialogue information, the character description information and the target memory, and inputting the dialogue reply prompt instruction into a configured dialogue large model, dialogue reply information output by the model is obtained and serves as the dialogue reply information of the virtual character to the current dialogue information. The emotion change information of the virtual character is stored in a memory form, continuous memory of the emotion of the virtual character is realized, so that a dialogue reply with richer and more smooth emotion expression can be generated, and the sense of reality of the virtual character is improved.

A method of managing access to a physical memory formed of n memory page frames using a set of virtual address spaces having n virtual address spaces each formed of a plurality p of contiguous memory pages. The method includes receiving a write request to write a block of data to a virtual address within a virtual address space i of the n virtual address spaces, the virtual address defined by the virtual address space i, a memory page j within that virtual address space i and an offset from the start of that memory page j; translating the virtual address to an address of the physical memory using a virtual memory table having n by p entries specifying mappings between memory pages of the virtual address spaces and memory page frames of the physical memory, wherein the physical memory address is defined by: (i) the memory page frame mapped to the memory page j as specified by the virtual memory table, and (ii) the offset of the virtual address; and writing the block of data to the physical memory address.

The invention discloses a memory forming method and a memory. The method comprises the following steps: providing a substrate; forming a device layer on the substrate, wherein the device layer comprises a storage unit; a first dielectric layer and a second dielectric layer are formed on the side, away from the substrate, of the device layer, the second dielectric layer is located on the side, away from the device layer, of the first dielectric layer, and the hydrogen content of the first dielectric layer is larger than that of the second dielectric layer; carrying out annealing treatment on the first dielectric layer and the second dielectric layer, wherein gas for annealing treatment comprises deuterium gas; and after annealing treatment, forming a first plug penetrating through the second dielectric layer, the first dielectric layer and the device layer. Through the arrangement of the technical characteristics, the control capability on hydrogen diffusion can be improved, so that the working performance of the memory is improved.

The invention relates to a sensor comprising a depth pixel having a controllable storage area which successively includes a potential barrier, a memory region, a pinch-off area; a transfer grid opposite the barrier; an inverse transfer grid opposite the barrier and the photosensitive region; a pinch-off grid opposite the memory forming a coupling capacitor with the memory. A charge flow path above the photosensitive region includes a collection area separated from the photosensitive region by a channel; and an initialization grid opposite the channel. A circuit is configured to: sample a signal from the memory; disconnect the pinch-off area and the capacitor; clear the memory by activating the inverse transfer and initialization grids; and read an electrical potential from the capacitor. (See Figure 3A for the abstract.)

An accelerator module includes a plurality of memories and a controller. The controller includes a plurality of memory controllers, a plurality of processing units, and a managing circuit. The plurality of memory controllers and the plurality of memories form a plurality of memory sub-channels. The plurality of processing units perform computational operations on a plurality of data stored in or read from the plurality of memories. The managing circuit redistributes tasks performed by the plurality of processing units or changes connections between the plurality of memory controllers and the plurality of processing units in response to a first memory sub-channel and a first processing unit being in a heavy-workload state.

The invention belongs to the technical field of electronics, and relates to an all-flash array for realizing inter-disk resource sharing based on hardware consistency interconnection. The all-flash array comprises a plurality of solid state disks; each solid state disk exposes a part of onboard memory through a CXL protocol, and the exposed onboard memory forms a global consistency memory domain, so that communication based on a shared memory can be carried out between the solid state disks; a solid state disk in an idle state is called as a creditor, the creditor calculates computing resources which can be borrowed, and availability of the computing resources is declared by writing idle resource descriptors; and calling the solid state disk lacking computing resources as a debtor, scanning idle resource descriptors of all other solid state disks by the debtor, and selecting at least one creditor to perform resource recovery so as to realize inter-disk resource sharing. According to the method, idle resources are utilized in a peak clipping and valley filling manner in a mode of sharing resources among disks in the all-flash array, so that the resource utilization rate can be improved.

The present application relates to a memory and a method for forming the same, the method comprising: providing a substrate; forming, in the substrate, a drain doped layer, a channel doped layer and a source doped layer which are sequentially stacked from inside of the substrate to a surface of the substrate; forming a bit line below the channel doped layer and at least partially in the drain doped layer, and a first isolation structure penetrating the bit line, the bit line and the first isolation structure extending along a first direction; forming, in the substrate, third isolation structures on both sides of the bit line extending along the first direction; and forming, in the substrate, a word line structure in the channel doped layer and a second isolation structure penetrating the word line structure, the word line structure and the second isolation structure extending along a second direction. The memory formed by the above method has improved storage density.

Some embodiments of the present application provide a memory forming method and a memory. The method includes: providing a substrate including at least word line structures and active regions, and bottom dielectric layers and bit line contact layers located on a top surface of the substrate, the bottom dielectric layer having bit line contact openings exposing the active regions in the substrate, and the bit line contact layers covering the bottom dielectric layers and filling the bit line contact openings; etching part of the bit line contact layers to form the bit line contact layers of different heights; forming conductive layers, top surfaces of the conductive layers being at the same height in a direction perpendicular to an extension direction of the word line structures; and the top surfaces of the conductive layers being at different heights in the extension direction of the word line structures; forming top dielectric layers.

The embodiment of the invention provides a data storage system, method and device of an edge node and a storage medium, and relates to the field of computers.The system comprises a dynamic memory, a storage type memory, a first solid state disk and a second solid state disk, first memory modules of the dynamic memory and the storage type memory form a first storage pool, and second memory modules of the storage type memory form a second storage pool; the first storage pool is used for storing node data of which the read-write probability is greater than a first threshold value, and the first memory module is a memory module addressing according to bytes in a storage type memory; the first solid state disk and a second memory module of the storage type memory form a second storage pool, the second storage pool is used for storing node data with the read-write probability smaller than or equal to the first threshold value and the read-write probability larger than the second threshold value, and the second memory module is a memory module addressing according to blocks in the storage type memory; the second solid state disk serves as a third storage pool and is used for storing node data with the read-write probability smaller than or equal to a second threshold value, and the second threshold value is smaller than the first threshold value.

The application discloses a kind of inter-core communication method, device, multi-core controller and computer readable storage medium.The method comprises: obtaining the data encoding information corresponding to target data, the data encoding information includes sending core mask and receiving core mask;The validity check is carried out to the data encoding information, and the validity check result is determined;When the validity check result is check pass, the authority check is carried out based on the sending core mask or the receiving core mask, and the authority check result is determined;When the authority check result is check pass, the target data is transmitted through the inter-core communication queue in target inter-core memory;The target inter-core memory is the inter-core memory related to the authority of the target data to the current core among the two inter-core memories formed between the current core and target core.The method can improve the security and efficiency of inter-core communication, and reduce the load of processor core with higher load.

An accelerator module includes a plurality of memories and a controller. The controller includes a plurality of memory controllers, a plurality of processing units, and a managing circuit. The plurality of memory controllers and the plurality of memories form a plurality of memory sub-channels. The plurality of processing units perform computational operations on a plurality of data stored in or read from the plurality of memories. The managing circuit redistributes tasks performed by the plurality of processing units or changes connections between the plurality of memory controllers and the plurality of processing units in response to a first memory sub-channel and a first processing unit being in a heavy-workload state.

The invention provides a memory, a memory forming method and a memory system, and relates to the technical field of semiconductor chips. The memory includes a first semiconductor structure and a second semiconductor structure coupled to the first semiconductor structure. The first semiconductor structure comprises a storage array, a word line and a bit line; wherein the memory array comprises a plurality of memory banks, and each memory bank comprises a plurality of memory blocks; the word lines and the bit lines are coupled with the storage blocks, the length direction of the word lines is a first direction, the length direction of the bit lines is a second direction, and the first direction is perpendicular to the second direction. The second semiconductor structure comprises a plurality of word line drivers corresponding to each storage block, and the word line drivers are coupled with the word lines; the word line driver includes a plurality of transistors arranged in a channel width direction of the transistors. The channel width direction of the transistor is perpendicular to the first direction. According to the embodiment of the invention, the size of the memory block in the length direction of the bit line can be reduced, so that the size of the memory is reduced.

System-in-packages (SiPs) having hybrid high bandwidth memory (HBM) devices, and associated systems and methods, are disclosed herein. In some embodiments, the SiP includes a base substrate, as well as a processing device and a hybrid high-bandwidth memory (HBM) device each carried by the base substrate. The processing device includes a processing unit and a first cache memory associated with a first level of a cache hierarchy. The hybrid HBM device is electrically coupled to the processing unit through a SiP bus in the base substrate. Further, the hybrid HBM device includes an interface die, one or more memory dies carried by the interface die, and a shared bus electrically coupled to the interface die and each of the memory dies. The hybrid HBM device also includes a second cache memory formed on the interface die that is associated with a second level of the cache hierarchy.

The invention relates to a cache memory in a vertically integrated memory system and associated systems and methods. A system-in-package (SiP) with hybrid high bandwidth memory (HBM) devices and associated systems and methods are disclosed herein. In some embodiments, the SiP includes a base substrate and a processing device and a hybrid high bandwidth memory (HBM) device carried by each free radical base substrate. A processing apparatus includes a processing unit and a first cache memory associated with a first level of a cache hierarchy. The hybrid HBM device is electrically coupled to the processing unit through a SiP bus in the base substrate. In addition, the hybrid HBM device includes an interface die, one or more memory dies carried by the interface die, and a shared bus electrically coupled to each of the interface die and the memory dies. The hybrid HBM device also includes a second cache memory formed on the interface die associated with a second level of the cache hierarchy.

A low-power memory device in which a NAND flash memory and a controller are connected to each other with a short wiring, the controller and a cache memory are connected to each other with a short wiring, and signal transmission delay is small is provided. For example, the NAND flash memory is formed using a Si transistor formed with a single crystal silicon substrate. Since an OS transistor can be formed by a method such as a thin-film method, the cache memory formed using the OS memory can be stacked over the NAND flash memory. When the NAND flash memory and the cache memory are formed in one chip, the NAND flash memory and the controller can be connected to each other with a short wiring, and the controller and the cache memory can be connected to each other with a short wiring.

This invention relates to the field of automated dialogue technology, specifically to a decision-making method for adaptive single-turn dialogue and task-oriented multi-turn dialogue. It includes: conducting dialogue within a user communication unit; a dialogue state memory unit storing the dialogue format, slot information, and dialogue state within the user communication unit to form memory data, which is then output to a dialogue input unit; and the dialogue input unit inputting a dialogue format into the user communication unit that differs from the format stored in the dialogue state memory unit. In this invention, the dialogue state memory unit stores the current dialogue format, facilitating the input of different dialogue formats and ensuring smooth switching between multiple different dialogue formats during the dialogue process, thus guaranteeing the overall fluency of the dialogue.

The invention provides a method for forming a multi-valued memory, which comprises the following steps of: forming a charge storage region in a semiconductor substrate, and forming a floating diffusion region at the upper part of the charge storage region; an annular vertical transfer transistor is formed around the floating diffusion region, and the spatial distance between any point of a channel region of the annular vertical transfer transistor and a gate dielectric layer of the annular vertical transfer transistor is smaller than a preset threshold value, so that silicon in the channel region of the floating diffusion region is completely exhausted, and the gate control capability is improved.

A memory and a forming method thereof, the forming method comprising: providing a substrate; forming a first mask layer on a surface of the substrate, a plurality of strip-shaped patterns being formed in the first mask layer; forming a second mask layer on the first mask layer, a plurality of first patterns and a plurality of second patterns being formed in the second mask layer, the plurality of first patterns being arrayed and overlapping the strip-shaped patterns, the plurality of second patterns covering end portions of the strip-shaped patterns; and etching layer by layer to the substrate with the first mask layer and the second mask layer as masks, so as to transfer the strip-shaped patterns, the first patterns and the second patterns into the substrate, and form a plurality of discrete active regions arrayed and a split groove corresponding to the first patterns and the second patterns. The memory formed by the method has improved reliability.

A "hybrid-derived cache" stores semi-structured data or unstructured text data in an in-memory mirror form and stores columns in another form such as a column-major format. The hybrid-derived cache can cache scalar type columns in a column-major format. The structure of the in-memory mirror form of the semi-structured data or unstructured text data enables access and / or enhanced access to perform path-based and / or text-based query operations. The hybrid-derived cache improves cache containment for performing query operations. The in-memory mirror form is used to compute queries in a transaction-consistent manner by using an invalidation vector that is used to determine when to retrieve the transaction-consistent persistent form of the semi-structured data or unstructured text data instead of the in-memory form.