Serdes architecture for 64B/66B conversion

Abstract

The invention provides a serdes architecture for 64B / 66B conversion. The serdes architecture comprises an XLGMII, a PCS layer and a PMA layer; the interface bit width of the PCS layer and the PMA layer is configured to be 66bit. According to the 64B / 6B conversion serdes architecture, the PCS and PMA interface data width is configured to be 66bit, so that the number of clocks in the PCS is reduced,the working frequency and logic complexity in the PCS are effectively reduced, the time sequence requirement of PCS internal digital design is reduced, the chip design cost can be effectively reduced, and the chip performance and reliability are improved.

Description

【Technical field】 [0001] The invention relates to the technical field of IP design of FPGA chips, in particular to a serdes architecture for 64B / 66B conversion. 【Background technique】 [0002] High Speed ​​Serial Transceiver (High Speed ​​Serial Transceiver) is an important functional part of high-speed chips including Field Programmable Gate Array (Field Programmable Gate Array, FPGA). PMA) and Physical Coding Sub-layer (Physical Coding Sub-layer, PCS) and other IP components. PCS supports the flexible Word Alignment function; Channel Bonding: to achieve channel alignment, CTC (Clock Tolerance Compensation): to achieve common functions such as compensating for the small frequency difference between the sending clock and the receiving clock. [0003] In serdes IP, 64B_66B codec is a common function that needs to be supported. In the architecture of the prior art, the sending side needs to switch the clock frequency through the tx buffer in the transmission transmission box...

AI Technical Summary

Problems solved by technology

[0005] In this structure, the interface between PCS and PMA is 64bit (16bit, 20bit, 32bit, 40bit) bit width, and the interface rate is the ratio of the high-speed differential line rate to the bit width. The internal processing of PCS includes two clock domains, and the gear module is required for clock domain Switching, data reintegration, bit width conversion, chip design complexity is relatively high

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