A fully parallel high throughput ldpc decoding method

Abstract

The invention discloses an all-parallel high-throughput LDPC decoding method. The method comprises the following steps: step 1, storing information received from a channel after performing quantification on the same for updating a subsequent variable node; step 2, updating the variable node; step 3, updating a check node; and step 4, when the information of the variable node and the information ofthe check node are updated, accomplishing the first time update iteration operation, and performing multiple times of update iteration, and obtaining decoding output via a symbol of an update value of the variable node. By adoption of the all-parallel high-throughput LDPC decoding method, the total clock number of the decoding algorithm is reduced, the throughput of information transmission is improved, the error code performance of a communication system is improved, meanwhile the use rate of the overall resources in an FPGA decoding algorithm implementation process so as to realize an all-parallel decoding structure.

Description

technical field [0001] The invention relates to the field of digital communication, in particular to an all-parallel high-throughput LDPC decoding method. Background technique [0002] For wireless communication, terminal equipment generally has the characteristics of small size, portability, and low energy consumption. The battery life of wireless devices is increasingly valued by people, so how to reduce the transmit power in the uplink communication and the receive power in the downlink communication has become a top priority for people. The inevitable result of reducing the transmit power is to reduce the signal-to-noise ratio of the receiver , making reception extremely difficult, and because LDPC (Low Density Parity Check Code, Low Density Parity Check Code) can work normally under the condition of sex-to-noise ratio close to the Shannon limit, it can be widely recognized. At this stage, the advent of the information age has prompted the rapid development of wireless ...

AI Technical Summary

Problems solved by technology

This method has a high throughput rate, but takes up more logic resources, which is not conducive to the occasion of FPGA implementation.

Patent 2 (universal high-speed LDPC code encoding method and encoder, CN201611136149.8, 2016) proposes an encoding method based on an optimized Gaussian elimination algorithm, which can work at a clock frequency of 270MHz on FPGA, and the throughput reaches 15.1Gbps, but this method only gives the encoding implementation, not the decoding method

Patent 3 (an FPGA-based high-speed adaptive DVB-S2LDPC decoder and decoding method, CN201610955524.5, 2016) provides a multi-rate compatible decoding method, and the maximum throughput rate of this method on XC7VX485T can reach 5Gbps, Resource consumption is 67%, but the method still fails to achieve maximum optimization in resources and throughput

Images