Parallel-serial conversion circuit

A conversion circuit and serial conversion technology, applied in the computer field, can solve the problems of large area and strict timing requirements, and achieve the effect of large application scope and simplified structure

Active Publication Date: 2017-12-05
LOONGSON TECH CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The invention provides a parallel-serial conversion circuit, which is used to solve the problems of strict timing requirements and large area in the existing parallel-serial conversion circuit

Method used

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Embodiment Construction

[0041] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments It is a part of embodiments of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.

[0042] like figure 1 and figure 2 As shown, when the existing parallel-to-serial conversion circuit performs parallel-to-serial conversion (taking eight to one as an example), a multi-level tree-shaped parallel-to-serial conversion circuit composed of multiple MUXs is established according to requirements, and each conversion path in the circuit...

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Abstract

The present invention provides a parallel-serial conversion circuit. The circuit comprises a phase inverter and N dynamic triggers, wherein N is identical to the number of the bits of received parallel data; the output ends of the N dynamic triggers are connected with the input end of the phase inverter; the data receiving end of the n-th dynamic trigger receives n-th-bit data in the N-bit parallel data; the clock signal receiving end of the n-th dynamic trigger receives n-th clock signals; the clock periods of the clock signals are the same as the update period of the N-bit parallel data; the high eclectic level of the clock signals does not overlap; the circuit structure of each dynamic trigger does not include the phase inverter; and the value of n is a positive integer from 1 to N. The structure of the parallel-serial conversion circuit provided by the invention is simplified, time sequence requirements on paths are lowered, and an area occupied by the circuit is decreased.

Description

technical field [0001] The invention relates to the field of computers, in particular to a parallel-to-serial conversion circuit. Background technique [0002] In the field of integrated circuits, when the processor in the chip processes data, it usually uses multi-digit binary numbers to process data in parallel to improve the computing power. However, when the chip outputs data externally, each pin of the chip can only output one pin. bit data. More pins will result in a larger chip area, and the chip area is proportional to the cost of making the chip. Therefore, in order to save money, the output parallel data needs to go through a parallel-to-serial conversion circuit before reaching the pins of the chip. Line data, and then output the serial data through a pin, thereby reducing the number of pins required. [0003] figure 1 It is a schematic diagram of an existing 8-to-1 parallel-to-serial conversion circuit, figure 2 for figure 1 Schematic diagram of the circuit...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03M9/00
CPCH03M9/00
Inventor 孟时光赵鹏飞杨宗仁
Owner LOONGSON TECH CORP
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