This invention discloses a channel
estimation device based on power
delay spectrum
estimation. First, resource particles for pilots are extracted from the
frequency domain resource grid for different physical channels, and LS channel
estimation is performed with the generated local pilots. Then, according to different physical channels, two strategies are employed: segmented calculation and inverted edge data, transforming the data into a power of 2 number of points. A radix-2 IFFT
fast algorithm is used to convert the channel estimate at the
pilot to the
delay domain. A power
delay spectrum window is calculated in the delay domain, and
noise reduction
processing is applied to the channel estimate at the
pilot in the delay domain. Finally, a radix-2 FFT
fast algorithm is used to interpolate and obtain the channel estimate in the full
frequency domain. The data is then integrated and output according to different physical channels. This invention balances performance and implementation complexity, handles delay and hardware resources, improves the
system's versatility, compatibility, portability, and
scalability, and effectively solves the channel estimation problem based on FPGA or ASIC implementations.