A time-domain sensing scheme is introduced for reading a
DRAM cell and bit lines are multi-divided for reducing parasitic loading. Thereby lightly loaded
bit line is quickly charged by a selected
memory cell when reading data “1”. The charged
voltage is amplified by a segment read circuit, which quickly changes an output of a block read circuit. In contrast, the
bit line is discharged when reading data “0”, so that impedance of the segment read circuit is increased, which slowly changes the output of a block read circuit. Hence, data “1” is arrived early but data “0” is not arrived to a latch circuit, because the latch is locked by a locking
signal based on data “1”. Furthermore storage
capacitor is reduced to drive short
bit line only. Additionally, various alternatives are described.