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Successive approximation register analog-digital converter

A successive approximation, analog-to-digital converter technology, applied in analog-to-digital conversion, instrument, code conversion, etc., can solve the problem of low working speed and achieve the effect of improving working speed

Active Publication Date: 2012-02-15
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] The problem solved by the present invention is to provide a successive approximation analog-to-digital converter and its conversion method to solve the problem of low working speed in the existing successive approximation analog-to-digital converter

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  • Successive approximation register analog-digital converter
  • Successive approximation register analog-digital converter

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Embodiment Construction

[0021] The inventor of the present invention finds that in the existing SAR ADC structure, every time an analog-to-digital conversion is completed, there is an unavoidable idle time in the whole working unit, which makes it difficult for the working speed of the SAR ADC to be higher than 5Msps (5 million samples per second) Second-rate). The reason is that, in the existing SAR ADC structure, the conversion time for completing an analog voltage to digital conversion consists of a sampling time P and a shift time T. Specifically, such as figure 1 and figure 2 As shown, the clock generation unit 140 receives an external main clock, and then generates sub-clocks such as synchronous latch clock LCKCMP and SAR logic control clock through frequency division. In the first two cycles of the main clock, the sample / hold circuit in the DAC unit 100 samples / holds the differential input signal Vin, and outputs the differential signal to the comparison unit 110 for amplification, comparis...

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Abstract

The invention provides a successive approximation register analog-digital converter which comprises a digital-analog conversion unit, a comparison unit, a successive approximation logic control unit, a shift register and decoding unit and a clock generation unit. The successive approximation register analog-digital converter also comprises a signal feedback unit. An input terminal of the signal feedback unit connects with an output terminal of the comparison unit. An output terminal of the signal feedback unit connects with an input terminal of the successive approximation logic control unit. The signal feedback unit receives a comparison result outputted by the comparison unit, generates a feedback signal, outputs the feedback signal to the successive approximation logic control unit to trigger the successive approximation logic control unit to control the shift register and decoding unit to carry out shift motion, a problem that a whole analog-digital converter has a segment of idle time after a traditional successive approximation analog-digital converter compares unit latch difference signals is avoided, and a work speed of the successive approximation analog-digital converter is effective raised.

Description

technical field [0001] The invention relates to the field of mutual conversion of digital and analog signals, in particular to a successive approximation analog-to-digital converter. Background technique [0002] In modern digital systems, it is often necessary to convert analog signals to digital signals. Therefore, an analog-to-digital converter (ADC) is an important module in the system configuration, and often has an important impact on the performance of the system. Compared with pipeline level, Sigma-Delta and other types of analog-to-digital converters, successive approximation register analog-digital converters (SAR ADC) have the advantages of low power consumption and small size, especially because of the manufacturing process Good compatibility with modern digital CMOS process, easy to implement at lower process cost, therefore, SAR ADC has obtained a wide range, such as portable battery-powered instrumentation, pen input quantizer, industrial control and data sign...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03M1/38
Inventor 陈杉张志军
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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