240 results about "Analog chip" patented technology

The invention discloses a band-gap reference source high-order curvature compensation method based on an operational amplifier, and belongs to the technical field of high-precision analog integrated circuit design, and the method comprises the steps: generating an absolute temperature proportion PTAT current and an absolute temperature complementary CTAT current; generating a high-order curvature compensation voltage based on the PTAT current and the CTAT current; amplifying the generated high-order curvature compensation voltage through an operational amplifier, and superposing the amplified high-order curvature compensation voltage to a band-gap reference output stage to obtain compensated band-gap reference output voltage; and carrying out band-gap reference output calibration on the compensated band-gap reference output voltage so as to ensure that the temperature drift coefficient of the output band-gap reference voltage in the preset temperature range is smaller than a preset threshold value. According to the invention, high-order elimination of base-emitter voltage nonlinearity can be realized in a wide temperature range, and a relatively low temperature coefficient and low noise are achieved.

The invention discloses an automatic layout generation method based on an experience module and a related device, and relates to the technical field of computers.The method comprises the steps that a template file is extracted, an independent device is generated based on the template file, and an experience module library is constructed based on the independent device; determining coordinate mapping and size constraints of the device, and performing multi-channel chip canvas hierarchical construction based on the coordinate mapping and size constraints of the device to obtain multi-channel chip canvas hierarchical representation; based on the empirical module library and the multi-channel chip canvas hierarchical representation, a reinforcement learning model is used for layout wiring, a target layout is obtained, and the reinforcement learning model comprises a state generation model, a value network and a strategy network. Layout and wiring of devices can be controlled more accurately, stray capacitance and resistance are effectively reduced, and the performance and reliability of an analog integrated circuit are effectively improved.

The invention belongs to the technical field of analog integrated circuit design and memory read-write, and provides a multi-valued RRAM read-write circuit with a write-and-read function. The multi-valued RRAM read-write circuit is a multi-port device capable of performing read-write simultaneously, in write operation, a low dropout regulator is utilized to provide voltage for the RRAM circuit and the standard resistance circuit, mirror current is generated, the resistance value of the RRAM is set to be the total resistance of the standard resistance circuit, an operational amplifier is connected into the circuit through a CMOS switch, and feedback is formed to stabilize the voltage at the two ends of the RRAM; and in the read operation, the CMOS switch is used for disconnecting the operational amplifier, and the voltage at the two ends of the RRAM device is directly read. Compared with an existing multi-valued read-write circuit, the multi-valued RRAM read-write circuit has the advantages that write-and-read multi-valued RRAM read-write is realized, and meanwhile, the read-write circuit is not separated, so that the write-in speed is increased, and the area of the read-write circuit is saved.

The invention discloses a multi-channel high-speed low-power-consumption successive approximation analog-to-digital converter, system and method, and relates to the technical field of analog integrated circuit design, the analog-to-digital converter comprises an M-bit auxiliary ADC, n N-bit main ADCs, a multiplexer and a digital error correction circuit, an M-bit non-binary digital code is obtained through quantization of the auxiliary ADC, and the N-bit non-binary digital code is obtained through quantization of the N-bit main ADCs. A group of N-M-bit non-binary digital codes are obtained through quantization of multiple paths of main ADCs respectively, then combination and binary conversion are carried out on M-bit non-binary digital codes and each group of N-M-bit non-binary digital codes through a digital error correction circuit, n groups of binary digital codes are obtained and output, and multi-channel sampling, quantization, conversion and output are achieved. The device has the characteristics of low power consumption, high conversion speed and high precision, and the conversion speed and precision can be improved while the characteristic of low power consumption is maintained.

The utility model provides a transient enhancement circuit applied to a low dropout regulator, and relates to the technical field of analog integrated circuits. The overvoltage detection circuit drives the charging and discharging circuit to charge the grid electrode of the power output tube to lower the output voltage when the output voltage of the low dropout linear regulator exceeds the first voltage threshold value, and meanwhile, the undervoltage detection circuit drives the charging and discharging circuit to charge the grid electrode of the power output tube to lower the output voltage when the output voltage is smaller than the second voltage threshold value. When the output voltage of the low dropout linear regulator changes instantly and rapidly along with a load or changes in a rapid jitter phenomenon of the input voltage, the charging and discharging circuit is driven to discharge the grid electrode of the power output tube so as to increase the output voltage. The low-dropout linear regulator can quickly and adaptively cooperate with a negative feedback loop included in the low-dropout linear regulator to realize a timely output voltage transient response adjustment effect, so that the corresponding output voltage can be effectively limited to a set threshold range and quickly recovered to a stable state.

The invention belongs to the technical field of analog integrated circuit design automation, and discloses an analog integrated circuit cross-process performance prediction method and system based on Transform transfer learning, and the method comprises the steps: 1, carrying out the preprocessing of analog integrated circuit sample data; 2, serializing the sample data according to a preset sequence, mapping each parameter into vector representation, adding a global abstract vector, and splicing according to a fixed sequence to form an input sequence; 3, encoding the input sequence to obtain an output sequence; 4, inputting the global features into the regression head network, and outputting a performance index prediction value; 5, training is carried out, network parameters obtained through pre-training of the source technology are migrated to the target technology, fine adjustment is carried out on part of network parameters of a target technology data set, and cross-technology performance prediction is achieved; and 6, performing forward reasoning on operational amplifier design parameters under a given target process according to the steps 2-4 to obtain a performance prediction result. The method improves the stability and efficiency of performance prediction.

The invention discloses an analog integrated circuit test method based on edge calculation, the method is executed by an edge node, and the method comprises the following steps: obtaining a step response waveform of an analog integrated circuit; extracting screening features from the step response waveform; determining an abnormal level and a test type of the screening feature; determining the demand level of the server for the original waveform data based on the abnormal level of the screening feature and the test type; and determining a sending strategy for sending the screening feature and the original waveform data to the server based on the demand level. According to the invention, waiting and repeated interaction of the server can be reduced, and test judgment efficiency and test throughput are improved.

The invention provides a low-delay level shift circuit, and belongs to the technical field of analog integrated circuit power management, the circuit comprises a level shift core circuit and an edge detection logic circuit, the level shift core circuit adopts a high-voltage-resistant LDMOS to complete conversion of different voltage domain signals on the basis of a traditional cross coupling structure, and the edge detection logic circuit is connected with the edge detection logic circuit. The edge detection logic circuit detects a fast falling edge of the level shift core circuit, and an output signal only related to the fast edge is obtained after logic operation. The low-delay level shift circuit provided by the invention has no static power consumption, the delay of the level shift circuit can be reduced to below 1ns, the delay time of the low-delay level shift circuit is obviously reduced compared with the delay time of a traditional two-stage cross coupling level shift circuit, and the low-delay level shift circuit is suitable for the field of SiC MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) driving with higher requirements on propagation delay.

The invention relates to the technical field of analog integrated circuits, and discloses a reference clock frequency multiplier circuit and a chip, and the reference clock frequency multiplier circuit comprises a phase discriminator, a charge pump, a loop filter, a voltage-controlled delay unit, a multiphase injection locked ring oscillator and an edge combiner. And the voltage-controlled delay unit, the phase discriminator, the charge pump and the loop filter form a multi-phase clock generator. The multi-phase injection clock signal is generated by adopting the voltage-controlled delay unit, and the multi-phase injection locking ring oscillator is further adopted as an input clock source of the edge combiner, so that the phase error of the multi-phase injection clock signal generated by the voltage-controlled delay unit is suppressed; therefore, a frequency multiplication clock signal with an accurate duty ratio and low noise is obtained.

The invention discloses a low-ripple closed-loop negative-voltage charge pump circuit in the technical field of analog integrated circuits, and the circuit comprises a charge pump closed-loop modulation circuit, the output end of the charge pump closed-loop modulation circuit is connected with the low-ripple negative-voltage charge pump circuit, and the low-ripple negative-voltage charge pump circuit is used for receiving positive power supply voltage input and outputting negative power supply voltage; the low-ripple negative-voltage charge pump circuit comprises a charge pump module, the first end of the charge pump module is connected with the first end of the positive power supply filter capacitor and the output end of the charge pump closed-loop modulation circuit, and the charge pump module outputs an output signal through the first end. By fixing the switching frequency of the low-ripple closed-loop negative-voltage charge pump circuit, the influence of switching noise on the system is reduced without repeatedly starting and stopping or changing the switching frequency of the charge pump, meanwhile, the size of a positive power supply is adjusted in a closed-loop mode through a negative feedback loop, and the voltage of the positive power supply of the charge pump is dynamically compensated. And the output voltage excursion of the traditional charge pump under large current is reduced.

The invention provides a reference voltage circuit and a DCDC converter, and relates to the technical field of semiconductors. The reference voltage circuit comprises a band-gap reference module and an operational amplifier module, the operational amplifier module is configured to enable the band-gap reference module to output initial reference voltage based on negative feedback operation, the operational amplifier module is configured with a first group of chopping switches, the band-gap reference module is configured with a second group of chopping switches, the first group of chopping switches has a first switching signal period, and the second group of chopping switches has a second switching signal period. The second group of chopping switches has a second switching signal period, and one of the first switching signal period and the second switching signal period is nested with the other one, so that error signals generated by the band-gap reference module and the operational amplifier module are reversely superposed; and the low-pass filtering module is configured to perform low-pass filtering on the initial reference voltage. According to the technical scheme, the reference voltage circuit meeting the requirement of a high-precision analog integrated circuit for the reference voltage can be obtained.

The invention discloses a clamping circuit of an error amplifier, which belongs to the field of analog integrated circuits and comprises an error amplifier EA, a low-voltage clamping circuit and a high-voltage clamping circuit. The error amplifier EA comprises a first-stage operational amplifier, the non-inverting input end of the first-stage operational amplifier is connected with feedback voltage VFB, the inverting input end of the first-stage operational amplifier is connected with reference voltage VREF, and the first-stage operational amplifier outputs VC voltage; the error amplifier EA is used for amplifying the change of the feedback voltage VFB; when the VFB is reduced or increased, the corresponding low-voltage clamping circuit or the high-voltage clamping circuit works, the output VC of the first-stage operational amplifier is clamped to the low-voltage clamping limit VclampL or the high-voltage clamping limit VclampH, the VC is controlled to be within a certain range, then clamping of the output current IEA of the error amplifier EA is achieved, quick response and stable adjustment of a loop are achieved, and meanwhile the function of protecting the circuit is achieved.

The invention relates to the technical field of analog integrated circuit design, and particularly discloses a segmented temperature compensation band-gap reference circuit capable of trimming low temperature drift, which comprises a starting circuit, a first-order temperature compensation voltage circuit, a first-order temperature compensation current circuit and a segmented temperature compensation voltage circuit, the starting circuit is used for filling a target current into the first-order temperature compensation voltage circuit during power-on, so that the first-order temperature compensation voltage circuit is separated from a degeneracy point; the first-order temperature compensation voltage circuit is used for providing band-gap reference voltage and providing bias current for the first-order temperature compensation current circuit and the segmented temperature compensation voltage circuit. The first-order temperature compensation current circuit is used for providing reference current and providing bias current for the segmented temperature compensation voltage circuit; and the segmented temperature compensation voltage circuit is used for superposing the generated compensation voltage onto the band-gap reference voltage so as to further reduce the temperature coefficient of the band-gap reference voltage. The temperature drift of the band-gap reference voltage can be reduced.

An optoelectronic module. In some embodiments, the optoelectronic module includes a substrate; a digital integrated circuit, on an upper surface of the substrate; a photonic integrated circuit, secured in a pocket of the substrate, the pocket being in the upper surface of the substrate; and an analog integrated circuit, on the photonic integrated circuit.

The invention discloses an anti-counterfeiting method based on analog integrated circuit trimming and a PUF circuit, and relates to the technical field of microelectronic integrated circuits, and the anti-counterfeiting method comprises the following steps: (1) a factory setting stage: trimming an analog integrated circuit, taking a digital trimming code as an anti-counterfeiting ID of the analog integrated circuit after trimming, and storing the anti-counterfeiting ID in a manufacturer server; and (2) a verification stage: the user sends the product ID to the manufacturer server for verification, and the manufacturer server returns a verification result. According to the invention, the integrated circuit can be effectively prevented from being counterfeited and pirated without adding excessive on-chip circuits, the safety and legality of the product are ensured, and the method has the characteristics of low cost and high reliability.

The invention belongs to the technical field of analog integrated circuits, and particularly relates to a high-speed high-dv / dt noise suppression level shift circuit. The circuit is used for the BUCK converter, a trigger is used for inputting a logic signal to provide a stable dv / dt noise elimination path, and the reliability of a device is improved; the auxiliary recovery circuit is used for ensuring accurate and rapid establishment of a pull-down current, the pull-down current is multiplexed as a dv / dt noise supplement transient enhancement circuit, in addition, even if the dv / dt noise is large, the S of the SR trigger generates a false trigger pulse, at the moment, the R-end pulse of the trigger covers the false trigger pulse, and the accuracy of transmission logic under high noise is ensured. According to the level shift circuit, the reliability of a device and the correctness of logic transmission under a high-noise condition are ensured.

Methods, systems, and computer-readable media are used in graph-based machine learning of analog integrated circuits (ICs). In a first aspect, functional device pairs in transistor-level circuits are detected and classified using a hybrid approach combining a subgraph isomorphism algorithm, such as VF2, with a trained relational-graph convolutional network (RGCN). The VF2 algorithm identifies candidate pairs and initial categories, while the RGCN filters false positives using link prediction scores, preserving category labels for validated pairs. In a second aspect, a relational GraphSAGE model performs multi-class link prediction on a heterogeneous graph with netlist and functional relation edge types, labeling device pairs into analog primitive categories without technology-dependent features and merging overlapping pairs into larger functional groups. In a third aspect, circuit performance is predicted using a hierarchy-aware graph neural network comprising an edge-conditioned convolution (ECC) layer and multiple Circuit graph isomorphism network layers corresponding to hierarchy levels of device groupings.

The present application relates to the field of analog integrated circuit technology, and particularly relates to a kind of sampling and holding circuit based on noise cancellation.The present application handles sampling noise by introducing noise cancellation technology, input signal is directly connected to the upper plate of C1, C1 samples during S1 switch is closed;The output end of operational amplifier is connected with the lower plate of C2 through S2 switch, C2 samples sampling noise during S2 switch is closed, C2 two ends are connected with C1 two ends through S3 switch, C1 and C2 share charge during S3 switch is closed;Dynamic operational amplifier output end is connected with latch at the same time, so as to use operational amplifier as the preamplifier of comparator.The present application effectively suppresses the deterioration of sampling noise under the condition of reducing sampling capacitor, and dynamic operational amplifier greatly reduces the power consumption and noise of sampling and holding after introducing operational amplifier, and C2=C3 can also be set to make the gain of dynamic operational amplifier in noise elimination stage and subsequent as comparator preamplifier be equal, further improve the precision of circuit.

The invention discloses a low-mismatch ultra-wideband active balun, which belongs to the technical field of analog integrated circuits and comprises a first-stage amplifier and a second-stage amplifier which are sequentially arranged. The first-stage amplifier adopts a differential structure, and finally conversion from a single-end signal to a constant-amplitude and anti-phase differential signal is achieved. The second-stage amplifier isolates the influence of a rear-stage load on a front stage, and the symmetry of differential signals is ensured. In the second-stage amplifier, a seventh NMOS transistor and a tenth NMOS transistor form positive feedback; by introducing the cross coupling capacitor, the gate-source voltage difference between the eighth NMOS transistor and the ninth NMOS transistor is increased, voltage recovery is formed, compared with a traditional active balun, the second-stage amplifier reduces phase and amplitude mismatch of an output signal through positive feedback, meanwhile, the bandwidth is expanded, and therefore the bandwidth is increased. And the grid source signal amplitude is increased by utilizing source electrode voltage recovery, the equivalent transconductance is enhanced, and the phase and amplitude of the output signal are further stabilized.

The application is suitable for the field of analog integrated circuit design, and provides an analog-digital converter, a readout circuit, an image sensor and an analog-digital conversion method. A first slope generation module in the analog-digital converter is configured to provide a first slope signal. A pixel signal quantization module is configured to quantize a pixel signal at a p-resolution according to the first slope signal to generate a first quantization result. A second slope generation module is configured to provide M reference slope signals; wherein the M reference slope signals adopt a mode of multiple resolutions and multiple slopes; the pixel signal quantization module is further configured to determine a target segment reference slope signal from the M reference slope signals according to the first quantization result, and to quantize the pixel signal at a target resolution corresponding to the target segment reference slope signal according to the target segment reference slope signal to generate a second quantization result. The analog-digital converter provided in the application embodiment solves the problem of slow quantization speed of the existing SS ADC.

The embodiment of the invention discloses a chip detection method and device, electronic equipment and a storage medium, and can solve the problem that the detection of a digital-analog chip is not accurate enough due to the fact that an existing chip possibly cannot reflect related functions in the digital-analog chip very accurately. Obtaining original simulation data of the to-be-tested chip; based on the original simulation data, a target test chip is run, the target test chip is a chip obtained after the programmable integrated circuit chip simulates the function of the current version of the chip to be tested, and the current version is a version after version iteration; in the running process of the target test chip, running indexes are collected, and the detection result of the to-be-tested chip is determined according to the running indexes.

The invention discloses a switched capacitor resistance improvement method, and belongs to the field of analog integrated circuits. When the conduction is reduced, the NMOS tube is used as a switch, and the gate end voltage of the switch is reduced from the power supply voltage VDD until the gate end voltage is close to the threshold voltage or even lower than the threshold voltage; when a PMOS (P-channel Metal Oxide Semiconductor) tube is used as a switch, the gate end voltage of the switch is increased from the ground GND until the gate end voltage is close to the threshold voltage or even higher than the threshold voltage. According to the invention, the low conduction voltage is adopted to carry out switch resistance switching, the generated channel charge is reduced, and the charge accumulated to the input / output end is correspondingly reduced. The threshold value of the switch MOS tube is correspondingly changed due to the conversion of the process corner and the temperature, and if the MOS tube is used as a switch, the MOS tube with the same size can be used for forming a diode connection method to form the switch voltage.

In order to solve the problem of low actual execution efficiency caused by frequent data update when debugging the chip interface of the ATE device in the prior art, the application provides a system, a method and an application for simulating the debugging interface of a chip, comprising: an input module, a debugging interface device and a chip to be tested; wherein the input module is used for inputting debugging instructions; the debugging interface device interacts with the input module to batch store the debugging instructions; the chip to be tested interacts with the debugging interface device to generate corresponding protocols according to any debugging instruction and the debugging interface device to test the chip to be tested; the system has the advantages of simple structure, and does not need to frequently update data to the DIO unit of the hardware, can batch update data, uniformly trigger transmission, and improves the execution efficiency of the ATE device simulating the debugging interface of the chip.

This invention belongs to the field of analog integrated circuit technology, specifically relating to a frequency adaptive circuit for downhole detection. This invention utilizes a closed-loop adaptive feedback mechanism, employing multiple excitation frequencies generated by a frequency generator to continuously match and adapt to the transducer's resonant frequency. When a set of excitation frequencies achieves the highest matching degree with the resonant frequency, the echo energy reaches its peak. The frequency generator is adaptively adjusted based on the excitation frequency corresponding to the maximum peak signal obtained during the detection phase, and this optimal excitation frequency is used to generate the excitation signal in subsequent operations, thus completing the adaptation between the excitation frequency and the resonant frequency. This invention effectively avoids the influence of downhole temperature and pressure changes on the transducer's resonant frequency, and combines high automation, good real-time performance, and high imaging quality.

The application belongs to the technical field of analog integrated circuits, and particularly relates to a time gain compensation circuit based on a sub-threshold region current source. The application utilizes a VTC structure to convert a sampling differential voltage into two different time level signals Tn and Tp through constant gain; then the application utilizes a TVC structure to control the charging and discharging time of the sub-threshold region current source by using the phase difference of the two time level signals, realizes the conversion from time to voltage, the gain thereof changes exponentially with the gate-source voltage of the current source, and finally realizes the exponential gain compensation of the voltage signal. In the conversion process of gain compensation by utilizing voltage-time and time-voltage twice conversion, the conversion linearity is not affected by the input amplitude, the input swing is large, and the TGC circuit area can be reduced without complex analog circuit structure, the integration of the ultrasonic analog front-end circuit is improved, and thus the size of the ultrasonic imaging probe is reduced.

The application discloses a conflict-aware automatic routing method and system for analog integrated circuits, and relates to the technical field of computers.The method comprises the following steps: constructing a minimum spanning tree based on layout file information of the analog integrated circuit, generating a topology of the analog integrated circuit based on the minimum spanning tree, and obtaining target topology information; performing access point planning processing based on the target topology information; performing initial path planning based on the target topology information and access point planning information, performing line network distribution on the initial path information based on a cross relationship graph, and obtaining initial path information after line network distribution; performing 3D monotonic routing processing on the initial path information after line network distribution; and performing enhanced routing processing based on 3D monotonic routing information by using an A algorithm, and obtaining target routing information of the analog integrated circuit.The application realizes reliable routing in a complex layout environment, and ensures that the routing result meets production process rules.

The invention discloses a wide-swing output stage circuit. The wide-swing output stage circuit comprises a substrate bias control unit and an output stage circuit, wherein the substrate bias control unit is used for generating substrate bias voltages VBP and VBN according to output swing requirements and outputting the substrate bias voltages VBP and VBN to the output stage unit, and the output stage unit generates output signals meeting the output swing requirements by accessing the substrate bias voltages. According to the scheme, the swing increasing circuit is simple in structure and convenient to control, high-voltage devices and expensive complex processes are not needed, high-swing output can be achieved by adopting a conventional common commercial CMOS process tape-out, under the condition that a power supply is not increased, the output swing of a processing signal is increased by adjusting the substrate voltage of the MOS transistor output by the operational amplifier, and therefore the signal processing efficiency is improved. The dynamic range of an analog integrated circuit designed by applying the operational amplifier of the type can be effectively improved, and the operational amplifier is very suitable for the design of a low-power-supply-voltage analog integrated circuit with a smaller deep submicron size.

The invention discloses a low-kick-back low-detuning dynamic comparator with cross coupling pair transistors and an operation method, and belongs to the technical field of analog integrated circuits. The comparator comprises a pre-amplification stage and a regeneration stage, the pre-amplification stage is composed of a reset module I, an offset elimination module, a cross coupling module and a pre-amplification module, and the regeneration stage is composed of a reset module II, an enabling module and a latch comparison module. According to the operation method, a complete period is divided into four stages of resetting, offset elimination, sampling and comparison, wherein key nodes are initialized in the resetting stage; in the offset elimination stage, offset voltage of the input geminate transistors is stored through a capacitor. In the sampling stage, an input signal is coupled with a stored offset voltage, and introduction of additional offset is avoided; in the comparison stage, a cross coupling module is used for regulating and controlling the discharge rate, kickback noise is restrained, the comparison precision is improved, and finally signal latching is completed through a regenerative-stage positive feedback mechanism.

The invention relates to the technical field of intelligent power driving in analog integrated circuits, in particular to a novel intelligent power driving chip high-side continuous power supply circuit which comprises a novel charge pump bootstrap power supply circuit and a charge pump capacitor Ccharge. According to the novel charge pump bootstrap power supply circuit, an oscillator is integrated at the control end of a voltage withstanding switch S2A, a clock signal CLK is generated through the oscillator to control on and off of the voltage withstanding switch S2A, meanwhile, the dV / dt state of a floating ground end HS of a charge pump circuit is detected, a dV / dt detection adaptive circuit is matched to generate a control signal of a voltage withstanding switch S1A, and the voltage withstanding switch S2A is controlled to be switched on and off. A high-side continuous power supply circuit is formed by combining charge pump diodes D1 and D2 and a charge pump capacitor Ccharge and continuously supplies power to a bootstrap capacitor Cboot; according to the novel charge pump bootstrap power supply circuit, a high-side integrated level shift circuit in the novel charge pump bootstrap power supply circuit is effectively prevented from working in a high-frequency state, and the dynamic power consumption of the circuit is remarkably reduced while the relatively high power supply efficiency is maintained.

This invention belongs to the field of analog integrated circuit design, and particularly relates to a low-dropout linear regulator with fast dynamic response and high stability. It includes: an error amplifier, a Class AB buffer stage circuit, an output power transistor, a positive feedback resistor compensation circuit, an undervoltage detection circuit, and a startup circuit. The Class AB buffer stage circuit is used to improve the transient characteristics of the low-dropout linear regulator, and the positive feedback resistor compensation circuit is used to improve the phase margin of the low-dropout linear regulator. This invention achieves fast dynamic response, essentially eliminates overshoot and undershoot phenomena, and significantly shortens the recovery time. It also maintains high stability while ensuring loop gain and includes undervoltage detection functionality to ensure smooth system startup.