154 results about "Analog chip" patented technology

The invention discloses an automatic layout generation method based on an experience module and a related device, and relates to the technical field of computers.The method comprises the steps that a template file is extracted, an independent device is generated based on the template file, and an experience module library is constructed based on the independent device; determining coordinate mapping and size constraints of the device, and performing multi-channel chip canvas hierarchical construction based on the coordinate mapping and size constraints of the device to obtain multi-channel chip canvas hierarchical representation; based on the empirical module library and the multi-channel chip canvas hierarchical representation, a reinforcement learning model is used for layout wiring, a target layout is obtained, and the reinforcement learning model comprises a state generation model, a value network and a strategy network. Layout and wiring of devices can be controlled more accurately, stray capacitance and resistance are effectively reduced, and the performance and reliability of an analog integrated circuit are effectively improved.

The invention belongs to the technical field of analog integrated circuit design and memory read-write, and provides a multi-valued RRAM read-write circuit with a write-and-read function. The multi-valued RRAM read-write circuit is a multi-port device capable of performing read-write simultaneously, in write operation, a low dropout regulator is utilized to provide voltage for the RRAM circuit and the standard resistance circuit, mirror current is generated, the resistance value of the RRAM is set to be the total resistance of the standard resistance circuit, an operational amplifier is connected into the circuit through a CMOS switch, and feedback is formed to stabilize the voltage at the two ends of the RRAM; and in the read operation, the CMOS switch is used for disconnecting the operational amplifier, and the voltage at the two ends of the RRAM device is directly read. Compared with an existing multi-valued read-write circuit, the multi-valued RRAM read-write circuit has the advantages that write-and-read multi-valued RRAM read-write is realized, and meanwhile, the read-write circuit is not separated, so that the write-in speed is increased, and the area of the read-write circuit is saved.

The invention belongs to the technical field of analog integrated circuit design automation, and discloses an analog integrated circuit cross-process performance prediction method and system based on Transform transfer learning, and the method comprises the steps: 1, carrying out the preprocessing of analog integrated circuit sample data; 2, serializing the sample data according to a preset sequence, mapping each parameter into vector representation, adding a global abstract vector, and splicing according to a fixed sequence to form an input sequence; 3, encoding the input sequence to obtain an output sequence; 4, inputting the global features into the regression head network, and outputting a performance index prediction value; 5, training is carried out, network parameters obtained through pre-training of the source technology are migrated to the target technology, fine adjustment is carried out on part of network parameters of a target technology data set, and cross-technology performance prediction is achieved; and 6, performing forward reasoning on operational amplifier design parameters under a given target process according to the steps 2-4 to obtain a performance prediction result. The method improves the stability and efficiency of performance prediction.

The invention discloses an analog integrated circuit test method based on edge calculation, the method is executed by an edge node, and the method comprises the following steps: obtaining a step response waveform of an analog integrated circuit; extracting screening features from the step response waveform; determining an abnormal level and a test type of the screening feature; determining the demand level of the server for the original waveform data based on the abnormal level of the screening feature and the test type; and determining a sending strategy for sending the screening feature and the original waveform data to the server based on the demand level. According to the invention, waiting and repeated interaction of the server can be reduced, and test judgment efficiency and test throughput are improved.

The invention provides a reference voltage circuit and a DCDC converter, and relates to the technical field of semiconductors. The reference voltage circuit comprises a band-gap reference module and an operational amplifier module, the operational amplifier module is configured to enable the band-gap reference module to output initial reference voltage based on negative feedback operation, the operational amplifier module is configured with a first group of chopping switches, the band-gap reference module is configured with a second group of chopping switches, the first group of chopping switches has a first switching signal period, and the second group of chopping switches has a second switching signal period. The second group of chopping switches has a second switching signal period, and one of the first switching signal period and the second switching signal period is nested with the other one, so that error signals generated by the band-gap reference module and the operational amplifier module are reversely superposed; and the low-pass filtering module is configured to perform low-pass filtering on the initial reference voltage. According to the technical scheme, the reference voltage circuit meeting the requirement of a high-precision analog integrated circuit for the reference voltage can be obtained.

The invention discloses a clamping circuit of an error amplifier, which belongs to the field of analog integrated circuits and comprises an error amplifier EA, a low-voltage clamping circuit and a high-voltage clamping circuit. The error amplifier EA comprises a first-stage operational amplifier, the non-inverting input end of the first-stage operational amplifier is connected with feedback voltage VFB, the inverting input end of the first-stage operational amplifier is connected with reference voltage VREF, and the first-stage operational amplifier outputs VC voltage; the error amplifier EA is used for amplifying the change of the feedback voltage VFB; when the VFB is reduced or increased, the corresponding low-voltage clamping circuit or the high-voltage clamping circuit works, the output VC of the first-stage operational amplifier is clamped to the low-voltage clamping limit VclampL or the high-voltage clamping limit VclampH, the VC is controlled to be within a certain range, then clamping of the output current IEA of the error amplifier EA is achieved, quick response and stable adjustment of a loop are achieved, and meanwhile the function of protecting the circuit is achieved.

Methods, systems, and computer-readable media are used in graph-based machine learning of analog integrated circuits (ICs). In a first aspect, functional device pairs in transistor-level circuits are detected and classified using a hybrid approach combining a subgraph isomorphism algorithm, such as VF2, with a trained relational-graph convolutional network (RGCN). The VF2 algorithm identifies candidate pairs and initial categories, while the RGCN filters false positives using link prediction scores, preserving category labels for validated pairs. In a second aspect, a relational GraphSAGE model performs multi-class link prediction on a heterogeneous graph with netlist and functional relation edge types, labeling device pairs into analog primitive categories without technology-dependent features and merging overlapping pairs into larger functional groups. In a third aspect, circuit performance is predicted using a hierarchy-aware graph neural network comprising an edge-conditioned convolution (ECC) layer and multiple Circuit graph isomorphism network layers corresponding to hierarchy levels of device groupings.

The present application relates to the field of analog integrated circuit technology, and particularly relates to a kind of sampling and holding circuit based on noise cancellation.The present application handles sampling noise by introducing noise cancellation technology, input signal is directly connected to the upper plate of C1, C1 samples during S1 switch is closed;The output end of operational amplifier is connected with the lower plate of C2 through S2 switch, C2 samples sampling noise during S2 switch is closed, C2 two ends are connected with C1 two ends through S3 switch, C1 and C2 share charge during S3 switch is closed;Dynamic operational amplifier output end is connected with latch at the same time, so as to use operational amplifier as the preamplifier of comparator.The present application effectively suppresses the deterioration of sampling noise under the condition of reducing sampling capacitor, and dynamic operational amplifier greatly reduces the power consumption and noise of sampling and holding after introducing operational amplifier, and C2=C3 can also be set to make the gain of dynamic operational amplifier in noise elimination stage and subsequent as comparator preamplifier be equal, further improve the precision of circuit.

The invention discloses a low-mismatch ultra-wideband active balun, which belongs to the technical field of analog integrated circuits and comprises a first-stage amplifier and a second-stage amplifier which are sequentially arranged. The first-stage amplifier adopts a differential structure, and finally conversion from a single-end signal to a constant-amplitude and anti-phase differential signal is achieved. The second-stage amplifier isolates the influence of a rear-stage load on a front stage, and the symmetry of differential signals is ensured. In the second-stage amplifier, a seventh NMOS transistor and a tenth NMOS transistor form positive feedback; by introducing the cross coupling capacitor, the gate-source voltage difference between the eighth NMOS transistor and the ninth NMOS transistor is increased, voltage recovery is formed, compared with a traditional active balun, the second-stage amplifier reduces phase and amplitude mismatch of an output signal through positive feedback, meanwhile, the bandwidth is expanded, and therefore the bandwidth is increased. And the grid source signal amplitude is increased by utilizing source electrode voltage recovery, the equivalent transconductance is enhanced, and the phase and amplitude of the output signal are further stabilized.

The embodiment of the invention discloses a chip detection method and device, electronic equipment and a storage medium, and can solve the problem that the detection of a digital-analog chip is not accurate enough due to the fact that an existing chip possibly cannot reflect related functions in the digital-analog chip very accurately. Obtaining original simulation data of the to-be-tested chip; based on the original simulation data, a target test chip is run, the target test chip is a chip obtained after the programmable integrated circuit chip simulates the function of the current version of the chip to be tested, and the current version is a version after version iteration; in the running process of the target test chip, running indexes are collected, and the detection result of the to-be-tested chip is determined according to the running indexes.

In order to solve the problem of low actual execution efficiency caused by frequent data update when debugging the chip interface of the ATE device in the prior art, the application provides a system, a method and an application for simulating the debugging interface of a chip, comprising: an input module, a debugging interface device and a chip to be tested; wherein the input module is used for inputting debugging instructions; the debugging interface device interacts with the input module to batch store the debugging instructions; the chip to be tested interacts with the debugging interface device to generate corresponding protocols according to any debugging instruction and the debugging interface device to test the chip to be tested; the system has the advantages of simple structure, and does not need to frequently update data to the DIO unit of the hardware, can batch update data, uniformly trigger transmission, and improves the execution efficiency of the ATE device simulating the debugging interface of the chip.

This invention belongs to the field of analog integrated circuit technology, specifically relating to a frequency adaptive circuit for downhole detection. This invention utilizes a closed-loop adaptive feedback mechanism, employing multiple excitation frequencies generated by a frequency generator to continuously match and adapt to the transducer's resonant frequency. When a set of excitation frequencies achieves the highest matching degree with the resonant frequency, the echo energy reaches its peak. The frequency generator is adaptively adjusted based on the excitation frequency corresponding to the maximum peak signal obtained during the detection phase, and this optimal excitation frequency is used to generate the excitation signal in subsequent operations, thus completing the adaptation between the excitation frequency and the resonant frequency. This invention effectively avoids the influence of downhole temperature and pressure changes on the transducer's resonant frequency, and combines high automation, good real-time performance, and high imaging quality.

The application discloses a conflict-aware automatic routing method and system for analog integrated circuits, and relates to the technical field of computers.The method comprises the following steps: constructing a minimum spanning tree based on layout file information of the analog integrated circuit, generating a topology of the analog integrated circuit based on the minimum spanning tree, and obtaining target topology information; performing access point planning processing based on the target topology information; performing initial path planning based on the target topology information and access point planning information, performing line network distribution on the initial path information based on a cross relationship graph, and obtaining initial path information after line network distribution; performing 3D monotonic routing processing on the initial path information after line network distribution; and performing enhanced routing processing based on 3D monotonic routing information by using an A algorithm, and obtaining target routing information of the analog integrated circuit.The application realizes reliable routing in a complex layout environment, and ensures that the routing result meets production process rules.

The invention discloses a low-kick-back low-detuning dynamic comparator with cross coupling pair transistors and an operation method, and belongs to the technical field of analog integrated circuits. The comparator comprises a pre-amplification stage and a regeneration stage, the pre-amplification stage is composed of a reset module I, an offset elimination module, a cross coupling module and a pre-amplification module, and the regeneration stage is composed of a reset module II, an enabling module and a latch comparison module. According to the operation method, a complete period is divided into four stages of resetting, offset elimination, sampling and comparison, wherein key nodes are initialized in the resetting stage; in the offset elimination stage, offset voltage of the input geminate transistors is stored through a capacitor. In the sampling stage, an input signal is coupled with a stored offset voltage, and introduction of additional offset is avoided; in the comparison stage, a cross coupling module is used for regulating and controlling the discharge rate, kickback noise is restrained, the comparison precision is improved, and finally signal latching is completed through a regenerative-stage positive feedback mechanism.

The invention relates to the technical field of intelligent power driving in analog integrated circuits, in particular to a novel intelligent power driving chip high-side continuous power supply circuit which comprises a novel charge pump bootstrap power supply circuit and a charge pump capacitor Ccharge. According to the novel charge pump bootstrap power supply circuit, an oscillator is integrated at the control end of a voltage withstanding switch S2A, a clock signal CLK is generated through the oscillator to control on and off of the voltage withstanding switch S2A, meanwhile, the dV / dt state of a floating ground end HS of a charge pump circuit is detected, a dV / dt detection adaptive circuit is matched to generate a control signal of a voltage withstanding switch S1A, and the voltage withstanding switch S2A is controlled to be switched on and off. A high-side continuous power supply circuit is formed by combining charge pump diodes D1 and D2 and a charge pump capacitor Ccharge and continuously supplies power to a bootstrap capacitor Cboot; according to the novel charge pump bootstrap power supply circuit, a high-side integrated level shift circuit in the novel charge pump bootstrap power supply circuit is effectively prevented from working in a high-frequency state, and the dynamic power consumption of the circuit is remarkably reduced while the relatively high power supply efficiency is maintained.

This invention belongs to the field of analog integrated circuit design, and particularly relates to a low-dropout linear regulator with fast dynamic response and high stability. It includes: an error amplifier, a Class AB buffer stage circuit, an output power transistor, a positive feedback resistor compensation circuit, an undervoltage detection circuit, and a startup circuit. The Class AB buffer stage circuit is used to improve the transient characteristics of the low-dropout linear regulator, and the positive feedback resistor compensation circuit is used to improve the phase margin of the low-dropout linear regulator. This invention achieves fast dynamic response, essentially eliminates overshoot and undershoot phenomena, and significantly shortens the recovery time. It also maintains high stability while ensuring loop gain and includes undervoltage detection functionality to ensure smooth system startup.

The present application belongs to the field of analog integrated circuit, and particularly relates to an RC oscillator without starting circuit. The present application uses Schmitt trigger as the comparator in the RC oscillator, and uses the hysteresis effect and positive feedback characteristics of the Schmitt trigger to reduce the influence of kickback noise. Meanwhile, a reset port is added to the Schmitt trigger, so that the working state of the input end of the RS flip-flop is simultaneously low when the circuit starts; and the two output signals of the RS flip-flop are respectively applied to the reset ends of the two Schmitt triggers through the delay control module, so that the reset signal of the Schmitt trigger cannot control the output result in advance before the input signal changes, and the timing error is avoided. The present application effectively solves the problems of the existing RC oscillator, such as the need of starting circuit and high noise.

The application discloses a kind of low mismatch ultra-wideband active balun, analog integrated circuit technical field, comprising: first-stage amplifier and second-stage amplifier arranged in sequence.The first-stage amplifier adopts differential structure, and finally realizes the conversion of single-ended signal to equal-amplitude differential signal.The second-stage amplifier isolates the influence of subsequent stage load on previous stage, and ensures the symmetry of differential signal.In the second-stage amplifier, seventh NMOS transistor and tenth NMOS transistor form positive feedback;by introducing cross-coupled capacitor, the gate-source voltage difference of eighth NMOS transistor and ninth NMOS transistor is increased, voltage recovery is formed, compared with traditional active balun, the second-stage amplifier of the application reduces the phase and amplitude mismatch of output signal by positive feedback at the same time, expands bandwidth, increases gate-source signal amplitude by using source voltage recovery, enhances equivalent transconductance, and further stabilizes the phase and amplitude of output signal.

An electronic load testing system is configured to emulate aspects of an integrated circuit (IC). A control module of the system is configured to be electrically coupled to a first location on a printed circuit board (PCB) of an electronic assembly, and a load module is configured to be electrically coupled to a second location on the PCB. The load module includes a load cell configured to selectively conduct current from a power supply of the electronic assembly. The first location and the second location are spaced apart and in electronic communication via one or more traces of the PCB. The control module is configured to communicate with the load module via the one or more traces of the PCB. In some examples, the load module and the IC have an equivalent form factor, such that the load module can be installed in place of the IC.

The invention discloses a temperature compensation band-gap reference circuit, relates to the technical field of analog integrated circuits, and aims to solve the problem that a traditional band-gap reference circuit is large in temperature drift due to the fact that the traditional band-gap reference circuit is affected by a VBE nonlinear high-order term within a wide temperature range. The circuit comprises a bias circuit module, a starting circuit module, a temperature compensation circuit module and a band gap core circuit module. Wherein the bias circuit module provides temperature-insensitive bias current for the system through the current mirror network; the starting circuit module realizes power-on quick starting, normal working zero static power consumption and power-down quick reset by utilizing the synergistic effect of a capacitor and a switch; according to the band-gap core circuit module and the temperature compensation circuit module, nonlinear voltage characteristics are extracted through triode emitter voltage difference, reverse compensation current is introduced through a feedback loop, and a high-order temperature drift item in reference voltage is accurately offset. In addition, the circuit adopts a composite resistor structure in which polycrystalline silicon and diffusion resistors are connected in series, so that process deviation and resistance temperature drift are further inhibited.

Disclosed in the present invention is a method for manufacturing a mirror-twin-structured integrated capacitor incorporating a low-noise and nonlinear-calibration process design. The method comprises the steps of: 1) growing a field oxide layer above a P-type well of an analog integrated circuit; 2) depositing a polycrystalline capacitor lower electrode plate polycrystalline film layer on a field oxide layer above an N-type well, and performing matched implantation doping; 3) growing a capacitor dielectric layer; 4) depositing a polycrystalline capacitor upper electrode plate polycrystalline film layer, and manufacturing a protective film layer and a protective structure. The mirror-twin-structured integrated capacitor incorporating a low-noise and nonlinear-calibration process design comprises a substrate, an N-type buried layer, a P-type buried layer, an epitaxial layer, an N-type well, a P-type well, a field oxide layer, a sacrificial oxide layer, a gate oxide layer, a polycrystalline thin film layer, a silicon dioxide dielectric layer, a silicon oxynitride dielectric layer, a low-dielectric-coefficient filling film layer, a metal interconnection film layer, and a passivation layer. The present invention reduces the impact of parasitic capacitance, substrate noise and crosstalk noise, and realizes the low noise characteristic of integrated capacitors.

This application provides a method, apparatus, electronic device, and storage medium for analyzing the top layer of a digital-to-analog chip. The method includes: determining first parameter information of metal line segments connected to a third-party module in the top layer of the digital-to-analog chip based on a chip layout data file of the top layer; determining antenna risk values ​​of connection nodes between the top layer of the digital-to-analog chip and the third-party module based on the first parameter information; when the antenna risk value is higher than a preset risk threshold, converting the chip layout data file into a first diagram structure and determining second parameter information between the third-party modules based on the first diagram structure; and analyzing antenna effects occurring at connection nodes between the top layer of the digital-to-analog chip and the third-party module based on the second parameter information. This application can perform analysis of the top layer of a digital-to-analog chip without using GDSII for antenna effect analysis.

The application discloses a low-temperature drift delay circuit for asynchronous timing, and relates to the technical field of analog integrated circuits, and aims at solving the problem of the conversion precision of a SAR ADC asynchronous timing circuit being reduced due to the influence of temperature on an existing delay circuit. At least, the low-temperature drift delay circuit comprises a temperature detection coding circuit, an inverter chain circuit and an adjusting tube circuit. The adjusting tube circuit is connected with the inverter chain circuit and the temperature detection coding circuit respectively, and the adjusting tube circuit comprises a plurality of parallelly connected NMOS tubes. The temperature detection coding circuit at least comprises a temperature sensor, a flash analog-digital converter and a digital coding logic circuit. The flash analog-digital converter is used for converting a temperature voltage signal into a thermometer code. The digital coding logic circuit is used for converting the thermometer code into a first control code, and the first control code is used for controlling the conduction and the cut-off of the NMOS tubes in the adjusting tube circuit. The low-temperature drift delay circuit provided by the application can adjust the delay time according to the temperature, and improve the conversion precision of the asynchronous timing circuit.

The invention relates to a Bayesian inference integrated circuit, referred to as a Bayesian circuit, for determining the probability of a signal S to be classified belonging to one of at least two behavior classes Ci, on the basis of at least one characteristic Fj of the signal S to be classified. The Bayesian circuit is based on spiking neurons.

Methods and systems for improved simulation of thermal characterization and thermal modeling of devices, such as smart phones, are described. In one embodiment, a method can characterize center, edge, and corner thermal decay behavior at different locations on a simulated IC. For each location, near and far field thermal effects are captured at the same time. A simulation system can generate a steady state thermal decay curve for each selected location that shows how the temperature changes with distance to a heat source. The system can then use a set of location dependent thermal decay curves to compute, based on an inputted power profile for the IC, a steady state thermal profile of the IC.

The invention relates to a low-temperature-drift segmented compensation band-gap reference circuit, and relates to the field of analog integrated circuit design. According to the technical scheme, by designing the linear segmentation compensation circuit, two segments of linear compensation currents matched with the temperature can be output, and the linear compensation currents are accurately overlaid on the parabola type temperature characteristic voltage with the downward opening output by the first-order compensation band-gap reference circuit. The two sections of compensation current respectively correspond to a low-temperature interval and a high-temperature interval to realize targeted compensation, an intermediate temperature area has no additional compensation interference, and the influence caused by high-order nonlinear temperature distortion is effectively counteracted through accurate adaptation and characteristic superposition of the temperature intervals. Compared with a traditional first-order compensation scheme, the temperature drift of the band-gap reference voltage can be remarkably restrained without a complex topological structure, the band-gap reference voltage source is suitable for wide-temperature-range application scenes, and a stable reference is provided for follow-up devices such as a low-dropout linear voltage stabilizer and a high-precision analog-digital converter.

The invention provides a PWM module design circuit for reducing dead time and a working method thereof, and belongs to the technical field of analog integrated circuits. Through cooperative work of the first lifting path and the second lifting path, the voltage of the VSUM node is quickly lifted at the voltage rising edge of the SW node. Therefore, the PWM comparator can make a response more quickly, output signals are overturned, and dead time which must be set for preventing straight-through of an upper power tube and a lower power tube is greatly shortened. The reduction of the dead time means that the effective conduction time of the power tube is increased, so that the switching loss is reduced, and the conversion efficiency of the whole power supply system is improved. And by delaying to start a time sequence control strategy of the M6, the dual-path automatic management is creatively realized. In the key initial stage of SW rising, M6 is not started; when the SW is stable, the M6 is turned on, the VSUM voltage is boosted to the state that the SW voltage is smaller than the breakover voltage of the body diode, the second boosted path is automatically cut off, and continuous electric leakage or invalid power consumption through the body diode in a steady state is avoided.

This invention relates to a digital calibration method and system for analog-to-digital converters (ADCs) based on an affine projection algorithm, belonging to the field of analog integrated circuits. Taking a split-type successive approximation ADC as an example, the method includes: obtaining the output difference between the first and second ADCs to be calibrated and defining it as an error signal; constructing a projection input matrix and an error vector based on the error signal and the digital code values ​​corresponding to the most recent P conversions; using an affine projection algorithm to output first and second update parameters to update the calibration parameters; and continuously updating the calibration parameters to make the performance indicators of the ADC to be calibrated continuously approach the ideal performance indicators until the error is within the allowable range. This invention constructs a projection input matrix from the digital code values ​​obtained from the current and several historical conversions, and adaptively updates the calibration parameters based on the affine projection algorithm, thereby achieving faster convergence and suppressing oscillations even when the input code pattern correlation is strong.

The invention discloses a low-power-consumption wide-voltage band-gap reference circuit, and relates to the field of analog integrated circuits. The reference source mainly comprises a starting circuit and a reference voltage generating circuit. The reference voltage generation circuit adopts a cascode current mirror structure to remarkably improve the power supply rejection ratio, and linearly superposes transistor VBE voltage with a negative temperature coefficient and voltage with a positive temperature coefficient in an output branch, so that high-precision reference voltage is output in a wide power supply voltage range; the starting circuit adopts a closed-loop self-adaptive detection framework, and core bias nodes of the reference generation circuit are symmetrically monitored in real time through an internal detection tube. In a zero-current degenerate state of circuit power-on, the starting circuit is conducted, and starting current is forcibly injected into the core network; when the reference establishes a steady-state working point, the change of the potential of the internal node enables the detection tube to automatically enter a cut-off state, and the starting branch is thoroughly cut off. According to the invention, high-reliability starting in a wide-voltage environment is realized, and the starting module has the characteristic of zero static power consumption in a steady state, so that the design requirements of a low-power-consumption and high-precision system are met.

The invention provides an analog integrated circuit layout method, system and device, a medium and a product, and relates to the technical field of integrated circuits, and the method comprises the steps: obtaining a target netlist, target circuit module attribute information and a target constraint condition description text of a to-be-designed analog integrated circuit, the target constraint condition description text is constructed based on a function design constraint condition of each target circuit module in the analog integrated circuit to be designed; inputting the target netlist, the target circuit module attribute information and the target constraint condition description text into a layout reasoning language model to obtain a target analog circuit layout layout corresponding to the to-be-designed analog integrated circuit output by the layout reasoning language model, the layout reasoning language model is obtained by training a visual language model based on sample data constructed by a thinking chain mechanism. The layout efficiency of the analog integrated circuit is remarkably improved, and the design quality is guaranteed.