328 results about "Analog chip" patented technology

The invention provides an analog integrated circuit layout method, device and equipment, a medium and an integrated circuit, and the method comprises the steps: obtaining an original layout diagram corresponding to the ith iteration based on the netlist information and a strategy network model of each electronic element needing to be arranged; when it is determined that i does not reach the first preset value, obtaining a value parameter of the original layout diagram corresponding to the ith iteration, updating a model parameter of the strategy network model based on the value parameter of the original layout diagram corresponding to the ith iteration, increasing i by 1, returning to execute the ith iteration calculation, and when it is determined that i reaches the first preset value, updating the model parameter of the strategy network model based on the value parameter of the original layout diagram corresponding to the ith iteration. Determining the original layout diagram corresponding to the ith iteration as a first intermediate layout diagram of each electronic component; and based on the netlist information of each electronic component, correcting the first intermediate layout diagram to obtain a target layout diagram of each electronic component. According to the invention, the reasonability and efficiency of the analog integrated circuit layout are effectively improved, and an automatic solution is provided for the analog integrated circuit layout.

The invention discloses a band-gap reference source high-order curvature compensation method based on an operational amplifier, and belongs to the technical field of high-precision analog integrated circuit design, and the method comprises the steps: generating an absolute temperature proportion PTAT current and an absolute temperature complementary CTAT current; generating a high-order curvature compensation voltage based on the PTAT current and the CTAT current; amplifying the generated high-order curvature compensation voltage through an operational amplifier, and superposing the amplified high-order curvature compensation voltage to a band-gap reference output stage to obtain compensated band-gap reference output voltage; and carrying out band-gap reference output calibration on the compensated band-gap reference output voltage so as to ensure that the temperature drift coefficient of the output band-gap reference voltage in the preset temperature range is smaller than a preset threshold value. According to the invention, high-order elimination of base-emitter voltage nonlinearity can be realized in a wide temperature range, and a relatively low temperature coefficient and low noise are achieved.

The invention provides a bidirectional level converter and electronic equipment, and relates to the technical field of analog integrated circuits, the bidirectional level converter comprises a first port, a second port and a conversion circuit arranged between the first port and the second port; the first port comprises a first input / output port and a first reference level port; the second port comprises a second input / output port and a second reference level port; the conversion circuit comprises a first Schmidt comparator, a clamping circuit, a pull-up module, a pull-down module and a second Schmidt compartment.The bidirectional level converter and the electronic equipment have the advantages that under the condition that an input signal is converted from a high signal to a low signal, driving of an input stage does not need extremely high driving capacity, input and output are in an isolated state, and the conversion efficiency is improved; and the load size of the output stage has no influence on the driving capability of the input stage, so that the integrity of signals can be maintained, the system design is more flexible, and meanwhile, the circuit can adapt to more application scenes.

The invention discloses an automatic layout generation method based on an experience module and a related device, and relates to the technical field of computers.The method comprises the steps that a template file is extracted, an independent device is generated based on the template file, and an experience module library is constructed based on the independent device; determining coordinate mapping and size constraints of the device, and performing multi-channel chip canvas hierarchical construction based on the coordinate mapping and size constraints of the device to obtain multi-channel chip canvas hierarchical representation; based on the empirical module library and the multi-channel chip canvas hierarchical representation, a reinforcement learning model is used for layout wiring, a target layout is obtained, and the reinforcement learning model comprises a state generation model, a value network and a strategy network. Layout and wiring of devices can be controlled more accurately, stray capacitance and resistance are effectively reduced, and the performance and reliability of an analog integrated circuit are effectively improved.

The invention belongs to the technical field of analog integrated circuit design and memory read-write, and provides a multi-valued RRAM read-write circuit with a write-and-read function. The multi-valued RRAM read-write circuit is a multi-port device capable of performing read-write simultaneously, in write operation, a low dropout regulator is utilized to provide voltage for the RRAM circuit and the standard resistance circuit, mirror current is generated, the resistance value of the RRAM is set to be the total resistance of the standard resistance circuit, an operational amplifier is connected into the circuit through a CMOS switch, and feedback is formed to stabilize the voltage at the two ends of the RRAM; and in the read operation, the CMOS switch is used for disconnecting the operational amplifier, and the voltage at the two ends of the RRAM device is directly read. Compared with an existing multi-valued read-write circuit, the multi-valued RRAM read-write circuit has the advantages that write-and-read multi-valued RRAM read-write is realized, and meanwhile, the read-write circuit is not separated, so that the write-in speed is increased, and the area of the read-write circuit is saved.

The invention discloses a multi-channel high-speed low-power-consumption successive approximation analog-to-digital converter, system and method, and relates to the technical field of analog integrated circuit design, the analog-to-digital converter comprises an M-bit auxiliary ADC, n N-bit main ADCs, a multiplexer and a digital error correction circuit, an M-bit non-binary digital code is obtained through quantization of the auxiliary ADC, and the N-bit non-binary digital code is obtained through quantization of the N-bit main ADCs. A group of N-M-bit non-binary digital codes are obtained through quantization of multiple paths of main ADCs respectively, then combination and binary conversion are carried out on M-bit non-binary digital codes and each group of N-M-bit non-binary digital codes through a digital error correction circuit, n groups of binary digital codes are obtained and output, and multi-channel sampling, quantization, conversion and output are achieved. The device has the characteristics of low power consumption, high conversion speed and high precision, and the conversion speed and precision can be improved while the characteristic of low power consumption is maintained.

The present disclosure relates to an integrated circuit optimization design device including an integrated circuit design generator configured to generate an integrated circuit design, a simulator configured to simulate the integrated circuit design, and an optimization engine configured to derive an optimal design parameter for the integrated circuit design by inputting a simulation result obtained from the simulator into an optimization model provided in advance, wherein the optimal design parameter includes asynchronous design information regarding the integrated circuit design generator, and the integrated circuit design generator asynchronously generates at least a part of the integrated circuit design according to the optimal design parameter to change the integrated circuit design. Thus, an optimal integrated circuit structure robust to process variations and capable of maximizing performance may be automatically generated by applying a design technology co-optimization (DTCO)-based design optimization technique that simultaneously takes into account a semiconductor manufacturing process and design optimization.

The invention belongs to the field of analog integrated circuit design, and particularly relates to a miniaturized high-precision non-binary R-2R DAC with digital correction. Non-binary characteristics are introduced by setting resistance values of bridge resistors RBm and RBm + 1, so that an LSB section is a binary weight section, and ISB and MSB are non-binary weight sections; therefore, the width-to-length ratios of the MOS tubes of the switches SWm + 1-SWm + i + j and SW1 are equal and do not need to be increased proportionally, the non-binary characteristic is further introduced by setting the switch on-resistance, the selection of the unit resistance R only needs to meet the matching precision of the LSB section, and the area of the switch resistor array is greatly reduced. Static errors in the ISB segment and the MSB segment are respectively corrected by using an OEM correction technology, only digital code redundancy between adjacent segments of the LSB segment, the ISB segment and the MSB segment needs to be obtained through measurement, redundant digital codes are removed by adjusting digital input codes of corresponding segments, and the m + n + k-1 bit binary DAC is obtained through calibration, so that the memory of a digital calibration algorithm is efficient, and the algorithm complexity is effectively reduced. According to the invention, the area of the DAC is obviously reduced while high precision is realized.

The utility model provides a transient enhancement circuit applied to a low dropout regulator, and relates to the technical field of analog integrated circuits. The overvoltage detection circuit drives the charging and discharging circuit to charge the grid electrode of the power output tube to lower the output voltage when the output voltage of the low dropout linear regulator exceeds the first voltage threshold value, and meanwhile, the undervoltage detection circuit drives the charging and discharging circuit to charge the grid electrode of the power output tube to lower the output voltage when the output voltage is smaller than the second voltage threshold value. When the output voltage of the low dropout linear regulator changes instantly and rapidly along with a load or changes in a rapid jitter phenomenon of the input voltage, the charging and discharging circuit is driven to discharge the grid electrode of the power output tube so as to increase the output voltage. The low-dropout linear regulator can quickly and adaptively cooperate with a negative feedback loop included in the low-dropout linear regulator to realize a timely output voltage transient response adjustment effect, so that the corresponding output voltage can be effectively limited to a set threshold range and quickly recovered to a stable state.

The invention belongs to the technical field of analog integrated circuit design automation, and discloses an analog integrated circuit cross-process performance prediction method and system based on Transform transfer learning, and the method comprises the steps: 1, carrying out the preprocessing of analog integrated circuit sample data; 2, serializing the sample data according to a preset sequence, mapping each parameter into vector representation, adding a global abstract vector, and splicing according to a fixed sequence to form an input sequence; 3, encoding the input sequence to obtain an output sequence; 4, inputting the global features into the regression head network, and outputting a performance index prediction value; 5, training is carried out, network parameters obtained through pre-training of the source technology are migrated to the target technology, fine adjustment is carried out on part of network parameters of a target technology data set, and cross-technology performance prediction is achieved; and 6, performing forward reasoning on operational amplifier design parameters under a given target process according to the steps 2-4 to obtain a performance prediction result. The method improves the stability and efficiency of performance prediction.

The invention relates to the technical field of circuit wiring, in particular to an AI-based circuit wiring system, method, medium and equipment, and the system comprises an input module, a preprocessing module, a deep learning module, a topology loss calculation module, a candidate layout generation module, a graphical user interface module, a man-machine interaction module and an output module. The input module is used for receiving each device of an analog circuit and physical size information thereof, and describing a description file of a topology constraint relationship between device pairs; the preprocessing module performs normalization processing on the size information of the device; the deep learning module is a graph structure neural network, and an output layer of the graph structure neural network outputs two-dimensional plane position coordinates corresponding to the devices; the topology loss calculation module defines a topology loss function and calculates an error value in a graph structure neural network training process, and the candidate layout generation module automatically generates a plurality of device candidate layout schemes meeting the topology loss function based on the trained graph structure neural network; the graphical user interface module is used for displaying candidate layout schemes and the error component value of each scheme; the man-machine interaction module provides a layout fine tuning function through a graphical user interface; the output module is used for outputting a final device layout scheme after manual fine tuning or automatic generation; according to the invention, the design efficiency and quality of the layout of the analog integrated circuit are improved, and the requirements of modern integrated circuit design for rapid iteration and efficient layout are met.

The invention relates to the technical field of analog integrated circuits, and discloses an LDO (Low Dropout Regulator) frequency compensation circuit based on a voltage-controlled current source, which comprises an input differential amplification module, a power regulation module, a frequency compensation module and a feedback voltage division module, and is characterized in that the output end of the input differential amplification module is electrically connected with the input end of the frequency compensation module; the frequency compensation module comprises a voltage-controlled current source and a compensation capacitor C1, the compensation capacitor C1 is matched with the voltage-controlled current source to adjust the loop frequency response, through a multi-stage current mirror and a Miller compensation network, pole distribution is optimized in a targeted mode, the Miller effect of the compensation capacitor C1 is matched, the dominant pole frequency can be actively lowered, a dominant pole is made to be away from a high-frequency area, and the loop phase margin is guaranteed; the self-excited oscillation is fundamentally suppressed, and the output voltage is stable and free of fluctuation.

The invention discloses an analog integrated circuit test method based on edge calculation, the method is executed by an edge node, and the method comprises the following steps: obtaining a step response waveform of an analog integrated circuit; extracting screening features from the step response waveform; determining an abnormal level and a test type of the screening feature; determining the demand level of the server for the original waveform data based on the abnormal level of the screening feature and the test type; and determining a sending strategy for sending the screening feature and the original waveform data to the server based on the demand level. According to the invention, waiting and repeated interaction of the server can be reduced, and test judgment efficiency and test throughput are improved.

The invention provides a low-delay level shift circuit, and belongs to the technical field of analog integrated circuit power management, the circuit comprises a level shift core circuit and an edge detection logic circuit, the level shift core circuit adopts a high-voltage-resistant LDMOS to complete conversion of different voltage domain signals on the basis of a traditional cross coupling structure, and the edge detection logic circuit is connected with the edge detection logic circuit. The edge detection logic circuit detects a fast falling edge of the level shift core circuit, and an output signal only related to the fast edge is obtained after logic operation. The low-delay level shift circuit provided by the invention has no static power consumption, the delay of the level shift circuit can be reduced to below 1ns, the delay time of the low-delay level shift circuit is obviously reduced compared with the delay time of a traditional two-stage cross coupling level shift circuit, and the low-delay level shift circuit is suitable for the field of SiC MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) driving with higher requirements on propagation delay.

The invention relates to the technical field of analog integrated circuits, and discloses a reference clock frequency multiplier circuit and a chip, and the reference clock frequency multiplier circuit comprises a phase discriminator, a charge pump, a loop filter, a voltage-controlled delay unit, a multiphase injection locked ring oscillator and an edge combiner. And the voltage-controlled delay unit, the phase discriminator, the charge pump and the loop filter form a multi-phase clock generator. The multi-phase injection clock signal is generated by adopting the voltage-controlled delay unit, and the multi-phase injection locking ring oscillator is further adopted as an input clock source of the edge combiner, so that the phase error of the multi-phase injection clock signal generated by the voltage-controlled delay unit is suppressed; therefore, a frequency multiplication clock signal with an accurate duty ratio and low noise is obtained.

The invention discloses an analog integrated circuit wiring method and system, electronic equipment and a storage medium, and the method comprises the steps: obtaining a preset net, and generating a minimum spanning tree according to the preset net; wherein the minimum spanning tree comprises a plurality of preset pin areas; determining pin priority data corresponding to the preset pin area according to a preset sorting mechanism; wherein the preset sorting mechanism is determined through a Manhattan distance algorithm; performing wiring planning through a mode wiring algorithm according to the pin priority data and the minimum spanning tree to obtain preset wiring data; performing design rule inspection on the preset wiring data to obtain an inspection result; and when it is determined that the inspection result is passed, generating a target wiring file according to preset wiring data. According to the embodiment of the invention, the wiring efficiency and quality of the analog integrated circuit can be effectively improved, so that the performance and reliability of the analog integrated circuit are improved. The circuit can be widely applied to the technical field of integrated circuits.

The invention discloses a low-ripple closed-loop negative-voltage charge pump circuit in the technical field of analog integrated circuits, and the circuit comprises a charge pump closed-loop modulation circuit, the output end of the charge pump closed-loop modulation circuit is connected with the low-ripple negative-voltage charge pump circuit, and the low-ripple negative-voltage charge pump circuit is used for receiving positive power supply voltage input and outputting negative power supply voltage; the low-ripple negative-voltage charge pump circuit comprises a charge pump module, the first end of the charge pump module is connected with the first end of the positive power supply filter capacitor and the output end of the charge pump closed-loop modulation circuit, and the charge pump module outputs an output signal through the first end. By fixing the switching frequency of the low-ripple closed-loop negative-voltage charge pump circuit, the influence of switching noise on the system is reduced without repeatedly starting and stopping or changing the switching frequency of the charge pump, meanwhile, the size of a positive power supply is adjusted in a closed-loop mode through a negative feedback loop, and the voltage of the positive power supply of the charge pump is dynamically compensated. And the output voltage excursion of the traditional charge pump under large current is reduced.

The invention provides a reference voltage circuit and a DCDC converter, and relates to the technical field of semiconductors. The reference voltage circuit comprises a band-gap reference module and an operational amplifier module, the operational amplifier module is configured to enable the band-gap reference module to output initial reference voltage based on negative feedback operation, the operational amplifier module is configured with a first group of chopping switches, the band-gap reference module is configured with a second group of chopping switches, the first group of chopping switches has a first switching signal period, and the second group of chopping switches has a second switching signal period. The second group of chopping switches has a second switching signal period, and one of the first switching signal period and the second switching signal period is nested with the other one, so that error signals generated by the band-gap reference module and the operational amplifier module are reversely superposed; and the low-pass filtering module is configured to perform low-pass filtering on the initial reference voltage. According to the technical scheme, the reference voltage circuit meeting the requirement of a high-precision analog integrated circuit for the reference voltage can be obtained.

The invention relates to the technical field of analog integrated circuits, in particular to an index curvature compensation band-gap reference source circuit and system. Comprising a band-gap core sub-circuit, an index curvature compensation sub-circuit, a power interface and a voltage interface, wherein the band-gap core sub-circuit is used for generating positive temperature coefficient current; and the index curvature compensation sub-circuit is used for receiving the positive temperature coefficient current so as to generate a base current and further output an index curvature compensation voltage to the voltage interface. According to the band-gap reference source circuit with the exponential curvature compensation, the positive temperature coefficient current of the band-gap core sub-circuit is converted into the base current through the exponential curvature compensation sub-circuit, so that the influence of a first-order item temperature coefficient and a high-order item temperature coefficient in the positive temperature coefficient current is eliminated; the exponential curvature compensation voltage which is not influenced by temperature drift is output, and the precision and the stability of the output voltage are improved.

The invention discloses a clamping circuit of an error amplifier, which belongs to the field of analog integrated circuits and comprises an error amplifier EA, a low-voltage clamping circuit and a high-voltage clamping circuit. The error amplifier EA comprises a first-stage operational amplifier, the non-inverting input end of the first-stage operational amplifier is connected with feedback voltage VFB, the inverting input end of the first-stage operational amplifier is connected with reference voltage VREF, and the first-stage operational amplifier outputs VC voltage; the error amplifier EA is used for amplifying the change of the feedback voltage VFB; when the VFB is reduced or increased, the corresponding low-voltage clamping circuit or the high-voltage clamping circuit works, the output VC of the first-stage operational amplifier is clamped to the low-voltage clamping limit VclampL or the high-voltage clamping limit VclampH, the VC is controlled to be within a certain range, then clamping of the output current IEA of the error amplifier EA is achieved, quick response and stable adjustment of a loop are achieved, and meanwhile the function of protecting the circuit is achieved.

The invention relates to the technical field of analog integrated circuit design, and particularly discloses a segmented temperature compensation band-gap reference circuit capable of trimming low temperature drift, which comprises a starting circuit, a first-order temperature compensation voltage circuit, a first-order temperature compensation current circuit and a segmented temperature compensation voltage circuit, the starting circuit is used for filling a target current into the first-order temperature compensation voltage circuit during power-on, so that the first-order temperature compensation voltage circuit is separated from a degeneracy point; the first-order temperature compensation voltage circuit is used for providing band-gap reference voltage and providing bias current for the first-order temperature compensation current circuit and the segmented temperature compensation voltage circuit. The first-order temperature compensation current circuit is used for providing reference current and providing bias current for the segmented temperature compensation voltage circuit; and the segmented temperature compensation voltage circuit is used for superposing the generated compensation voltage onto the band-gap reference voltage so as to further reduce the temperature coefficient of the band-gap reference voltage. The temperature drift of the band-gap reference voltage can be reduced.

An optoelectronic module. In some embodiments, the optoelectronic module includes a substrate; a digital integrated circuit, on an upper surface of the substrate; a photonic integrated circuit, secured in a pocket of the substrate, the pocket being in the upper surface of the substrate; and an analog integrated circuit, on the photonic integrated circuit.

The invention discloses an anti-counterfeiting method based on analog integrated circuit trimming and a PUF circuit, and relates to the technical field of microelectronic integrated circuits, and the anti-counterfeiting method comprises the following steps: (1) a factory setting stage: trimming an analog integrated circuit, taking a digital trimming code as an anti-counterfeiting ID of the analog integrated circuit after trimming, and storing the anti-counterfeiting ID in a manufacturer server; and (2) a verification stage: the user sends the product ID to the manufacturer server for verification, and the manufacturer server returns a verification result. According to the invention, the integrated circuit can be effectively prevented from being counterfeited and pirated without adding excessive on-chip circuits, the safety and legality of the product are ensured, and the method has the characteristics of low cost and high reliability.

The invention belongs to the technical field of analog integrated circuits, and particularly relates to a high-speed high-dv / dt noise suppression level shift circuit. The circuit is used for the BUCK converter, a trigger is used for inputting a logic signal to provide a stable dv / dt noise elimination path, and the reliability of a device is improved; the auxiliary recovery circuit is used for ensuring accurate and rapid establishment of a pull-down current, the pull-down current is multiplexed as a dv / dt noise supplement transient enhancement circuit, in addition, even if the dv / dt noise is large, the S of the SR trigger generates a false trigger pulse, at the moment, the R-end pulse of the trigger covers the false trigger pulse, and the accuracy of transmission logic under high noise is ensured. According to the level shift circuit, the reliability of a device and the correctness of logic transmission under a high-noise condition are ensured.

The invention belongs to the field of analog integrated circuit design, and particularly relates to an analog-to-digital converter applying auxiliary nested sampling noise elimination. According to the invention, an auxiliary nested sampling noise elimination circuit is introduced into an analog-to-digital converter circuit, and a storage capacitor is placed in a branch circuit by using an auxiliary amplifier, so that the elimination of KT / C noise is realized. Therefore, the problem of saturation of the storage capacitor can be avoided while the bandwidth of the amplification path is not attenuated; in addition, due to the design of the nested loop, the loop gain is improved, and the KT / C noise elimination performance is remarkably improved. According to the invention, technologies of an auxiliary amplifier, a nested loop, split sampling and the like are combined and used, so that efficient and high-speed KT / C elimination is realized; compared with a traditional high-precision SAR ADC, the driving pressure of a capacitor array is greatly relieved, the brand-new auxiliary nested sampling noise elimination circuit provides possibility for increasing the speed of the high-precision SAR ADC, and therefore an excellent solution is provided for the high-precision high-speed SAR ADC.

Methods, systems, and computer-readable media are used in graph-based machine learning of analog integrated circuits (ICs). In a first aspect, functional device pairs in transistor-level circuits are detected and classified using a hybrid approach combining a subgraph isomorphism algorithm, such as VF2, with a trained relational-graph convolutional network (RGCN). The VF2 algorithm identifies candidate pairs and initial categories, while the RGCN filters false positives using link prediction scores, preserving category labels for validated pairs. In a second aspect, a relational GraphSAGE model performs multi-class link prediction on a heterogeneous graph with netlist and functional relation edge types, labeling device pairs into analog primitive categories without technology-dependent features and merging overlapping pairs into larger functional groups. In a third aspect, circuit performance is predicted using a hierarchy-aware graph neural network comprising an edge-conditioned convolution (ECC) layer and multiple Circuit graph isomorphism network layers corresponding to hierarchy levels of device groupings.

The present application relates to the field of analog integrated circuit technology, and particularly relates to a kind of sampling and holding circuit based on noise cancellation.The present application handles sampling noise by introducing noise cancellation technology, input signal is directly connected to the upper plate of C1, C1 samples during S1 switch is closed;The output end of operational amplifier is connected with the lower plate of C2 through S2 switch, C2 samples sampling noise during S2 switch is closed, C2 two ends are connected with C1 two ends through S3 switch, C1 and C2 share charge during S3 switch is closed;Dynamic operational amplifier output end is connected with latch at the same time, so as to use operational amplifier as the preamplifier of comparator.The present application effectively suppresses the deterioration of sampling noise under the condition of reducing sampling capacitor, and dynamic operational amplifier greatly reduces the power consumption and noise of sampling and holding after introducing operational amplifier, and C2=C3 can also be set to make the gain of dynamic operational amplifier in noise elimination stage and subsequent as comparator preamplifier be equal, further improve the precision of circuit.

The present invention belongs to the technical field of integrated circuits, particularly the DAC circuit in analog integrated circuits. Specifically, it is a rail-to-rail current-steering DAC structure with a self-calibration function, including a digital input register, a decoder, a PMOS current source differential driver, an NMOS current source differential driver, a PMOS current source, an NMOS current source, a digital pre-calibration module, and a strobe switch. The digital input register receives an external digital input and transmits it to the decoder. After decoding the input digital signal, the decoder transmits the digital signal to the PMOS current source differential driver and the NMOS current source differential driver. The PMOS current source differential driver and the NMOS current source differential driver are respectively connected to the PMOS current source and the NMOS current source. The digital pre-calibration module is connected to the PMOS current source and the NMOS current source. The strobe switch is connected to the PMOS current source and the NMOS current source.

The invention discloses a low-mismatch ultra-wideband active balun, which belongs to the technical field of analog integrated circuits and comprises a first-stage amplifier and a second-stage amplifier which are sequentially arranged. The first-stage amplifier adopts a differential structure, and finally conversion from a single-end signal to a constant-amplitude and anti-phase differential signal is achieved. The second-stage amplifier isolates the influence of a rear-stage load on a front stage, and the symmetry of differential signals is ensured. In the second-stage amplifier, a seventh NMOS transistor and a tenth NMOS transistor form positive feedback; by introducing the cross coupling capacitor, the gate-source voltage difference between the eighth NMOS transistor and the ninth NMOS transistor is increased, voltage recovery is formed, compared with a traditional active balun, the second-stage amplifier reduces phase and amplitude mismatch of an output signal through positive feedback, meanwhile, the bandwidth is expanded, and therefore the bandwidth is increased. And the grid source signal amplitude is increased by utilizing source electrode voltage recovery, the equivalent transconductance is enhanced, and the phase and amplitude of the output signal are further stabilized.

The application is suitable for the field of analog integrated circuit design, and provides an analog-digital converter, a readout circuit, an image sensor and an analog-digital conversion method. A first slope generation module in the analog-digital converter is configured to provide a first slope signal. A pixel signal quantization module is configured to quantize a pixel signal at a p-resolution according to the first slope signal to generate a first quantization result. A second slope generation module is configured to provide M reference slope signals; wherein the M reference slope signals adopt a mode of multiple resolutions and multiple slopes; the pixel signal quantization module is further configured to determine a target segment reference slope signal from the M reference slope signals according to the first quantization result, and to quantize the pixel signal at a target resolution corresponding to the target segment reference slope signal according to the target segment reference slope signal to generate a second quantization result. The analog-digital converter provided in the application embodiment solves the problem of slow quantization speed of the existing SS ADC.