This invention discloses a unified vector timing construction method for
ripple optimization of multi-parallel
converters. This method constructs a near-three-
voltage vector set based on a reference
voltage and generates a basic vector sequence
library by progressively varying the total number of conducting switching devices in parallel branches, forming a unified modulation framework applicable to any number of parallel
converters. Based on the basic vector sequence
library, a symmetrical vector timing unit is constructed, and by repeatedly expanding this basic unit, a complete vector timing sequence applicable to any number of parallel
converters is formed. Furthermore, the switching timing sequence of each parallel
branch is determined based on the complete vector timing sequence. Two types of triangular carrier initial angle configuration schemes and two complementary modulation
waves and their corresponding operating
modes are proposed to generate the switching timing sequence of each parallel
branch. This method optimizes output current
ripple while providing modulation
degrees of freedom for optimizing other performance indicators.