The invention discloses a
fault model construction method for adaptive testing of abnormal values of a
system-on-
chip. The method relates to the technical field of fault construction of
chip testing, and comprises the following steps: testing chips on a large scale under the conditions of different temperatures, voltages, frequencies, loads and the like, acquiring performance parameters such as
signal delay and
power consumption, screening abnormal values by applying a Z-
score or box plot method, and
processing by using a sliding window; extracting features through CNN or RNN, and normalizing the features; fault features are classified through K-Means or
hierarchical clustering, and the accuracy rate is larger than or equal to 80%; a model is built through an SVM or a
decision tree, faults can be predicted, self-updating can be achieved, self-adaptive adjustment can be achieved according to
chip parameter changes,
independent data verification optimization, one-out-of-leave evaluation and
gradient descent optimization are achieved. According to the method, multi-condition testing can be carried out on the
system-level chip, abnormal values are accurately screened, features are extracted, faults are classified, a
fault model capable of being self-updated is constructed, self-adaptive adjustment and
verification optimization are achieved, the accuracy is improved, and the chip testing and fault diagnosis efficiency and accuracy are improved.