920 results about "Circuit Failure" patented technology

The invention discloses a current-magnitude-based open-circuit failure online-diagnosis method for a power tube of an inverter, belongs to the field of motor control, and aims to solve the problem of poor robustness of a current-magnitude-based open-circuit failure diagnosis technology for the power tube of the inverter. The method comprises the following steps of establishing a current observer model of a permanent magnet synchronous motor driving system in a failure-free state, comparing an observed current value with detection current to obtain a three-phase current residual, converting the three-phase current residual to a two-phase coordinate system in a coordinate conversion way to obtain a current residual vector, standardizing the current residual vector, and diagnosing and positioning an open-circuit failure of the power tube of the inverter according to the amplitude and the phase of the standardized current residual vector. The current-magnitude-based open-circuit failure online-diagnosis method for the power tube of the inverter is free of influence of a system closed-loop control algorithm and insensitive to loads, and has higher robustness to parameter errors, measurement errors, system disturbance and the like.

Short circuit failures and open circuit failures of light-emitting elements used for the backlight in an LCD panel can be reliably and easily detected. The voltage at the node between each series-connected light-emitting element array and a drive circuit is detected as a monitored voltage. A maximum detector detects the highest and a minimum detector detects the lowest of these monitored voltages. Short circuit or open circuit failure of a light-emitting element is detected by comparing the voltage difference between the maximum detector output and the minimum detector output with a specific reference voltage.

A prognostic cell is used to predict impending failure of a useful circuit or circuits in a host IC. Increasing the stress on the prognostic cell relative to the useful circuit shifts the failure distribution of the cell along the time axis. The relative amount of time between the useful circuit failure and prognostic cell trigger point is the “prognostic distance”. The prognostic distance is controlled by designing in the excess stress applied in test device(s), by setting the threshold for triggering in the comparison circuit or by both. Prediction accuracy is enhanced by using multiple test devices to oversample the underlying failure distribution and triggering the failure indicator when a certain fraction fail.

The invention relates to a stereoscopic vision based emergency treatment device and method for running vehicles, wherein the device comprises a binocular-vision image pick-up unit, an on-board bus interface, a central processing unit, a vehicle braking control system and an acousto-optic alarm circuit. The binocular-vision image pick-up unit is used for capturing an image of a road in front of a vehicle; the DSP (digital signal processor) based central processing unit is adopted for carrying out real-time quick calculation on a visual image so as to obtain a three-dimensional road scene, and compares the obtained three-dimensional road scene with a safe driving road model set up by a system so as to judge whether obstacles or dangers exist in the traveling direction of the vehicle; when adanger is found, the vehicle braking control system is started so as to reduce the speed of the vehicle and send an acousto-optic alarm to a driver; meanwhile, the central processing unit is connected with a vehicle sensor by an inter-vehicle bus so as to detect the state of the vehicle, and when the vehicle has mechanical or circuit faults, a braking system is started so as to reduce the speed of the vehicle and send an acousto-optic alarm. The device disclosed by the invention can be arranged on ordinary motor vehicles so as to avoid the occurrence of accidents or reduce the accident loss, thereby improving the driving safety performance.

The invention discloses an analog circuit dynamic online failure diagnosing method based on GSD-SVDD, belonging to the technical field of analog circuit failure diagnosis. In an offline test process, a KFCM algorithm is adopted to calculate a failure resolution value of each testable node and an optimal test node set is selected according to the failure resolution value. In an online diagnosis process, a failure diagnosis model is established by adopting an SVDD single classification approach based on a map spatial distance positive and negative sample weighting, test samples are diagnosed by a layered diagnosis method, and a failure class library and the diagnosis model are renewed dynamically. The method effectively reduces the drill and online diagnosis time of the diagnosis model, guarantees the real-time property of the online diagnosis and improves the precision of the failure diagnosis and can dynamically renew parameters of the diagnosis model so as to enable the a diagnosis system to have the self-adaption capability.

The invention discloses a sub-module fault diagnosis method of a modular multilevel converter in the technical field of power transmission and distribution. According to the technical scheme, the method includes: firstly, performing fault feature analysis aiming at typical faults of sub-modules; secondly, configuring an SFDU (sub-module fault diagnosis unit) in an SMC (sub-module controller), and combining provided sub-module fault diagnosis indexes by the aid of capacitor voltage, bridge arm current and trigger signals at the moment so as to achieve diagnosis of faults of sub-module IGBT (insulated gate bipolar translator) short circuit, IGBT open circuit, FWD (freewheel diode) short circuit, capacitor failure and the like; and finally, adopting an exclusive method in a VBC (valve base controller) to achieve diagnosis of faults of sub-module FWD open circuit, capacitor open circuit failure, connection line open circuit and the like. The method has the advantages that diagnosis of sub-module faults is achieved on the base of software, additional measuring points are not added to an original control protection system, and the method is easy to implement, has quick and efficient sub-module fault diagnosis capability, and has coordination with other protection settings.

A method and system are provided for automatically rerouting logical circuit data from a physical circuit failure in a data network. When a failure in a logical circuit is detected, a label or services name associated with the logical circuit is automatically associated with a logical circuit identifier utilized for identifying the logical circuit in the data network. Once the logical circuit is associated with the logical circuit identifier, the logical circuit data may be automatically rerouted to a “failover network,” thereby minimizing lost data until the failure in the logical circuit is resolved. The logical failover circuit may be an already existing logical circuit provisioned over a dedicated backup physical circuit in the data network.

The invention discloses a method for recovering networks in a ring network. Ethernet switch equipment enters a communication status after an initial configuration and precise time synchronization based on an IEEE 1588 protocol. Each equipment according to the configuration of the network sends out time-sharing equipment statement messages and link circuit checking messages. The link circuit checking messages are sent by a multicast address in two ways; if a port of equipment receives no link checking messages of a connected port after the time out, then a network trouble can be determined and link circuit alarm messages are sent by the multicast address in two ways for alarming. The rest equipments in the ring network after receiving the link circuit alarm message, then empty an FDB list and utilize a backup link circuit to restart path learning. By adopting the method of the invention, any communication link circuit failure in the ring network can be quickly detected and correspondingly processed, thereby meeting the availability requirements of Ethernet communication by the industrial automatic field.

The invention discloses a shift registering unit, a shift register, a driving method of the shift register and a display device. The shift registering unit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, a first capacitor, a second capacitor, a third capacitor, an input signal end, a first clock signal end, a second clock signal end, a first voltage signal end, a second voltage signal end and a first output end. According to the invention, shift output of grid signals can be achieved via quite few transistors, power consumption of the shift register is reduced; a circuit failure caused by potential competence of nodes and threshold value drifting of the transistors can be avoided; and stability of circuit operation is enhanced.

The invention relates to a high/low voltage switching excitation system of an electromagnetic flowmeter with a bypass and an energy feedback circuit. The excitation system comprises an adjustable low voltage source circuit, a high/low voltage switching circuit, a constant-current circuit, a bypass circuit, an H-bridge excitation circuit, an excitation control circuit, a logic switching circuit, apower supply detection circuit, the energy feedback circuit and an energy leakage circuit. A practical excitation current detected on a current detecting resistor is compared with an excitation current threshold set in the logic switching circuit, thereby obtaining a control logic which is used for controlling the high/low voltage switching circuit and the bypass circuit, so as to select an excitation work voltage; introduction of the bypass circuit accelerates the response velocity of the excitation current in a coil obviously; the energy feedback circuit stores the energy fed back from an excitation coil; the power supply detection circuit, the energy leakage circuit and a switching protection circuit perform electrification, outage and error protection on the excitation system. The excitation system related to the invention improves the utilization rate of power supply, accelerates the response speed of excitation current, broadens the range of excitation frequency and provides circuit fault protection.

The invention provides a Saber-based circuit failure simulation analyzing method. The method is characterized by comprising the following steps: 1, performing Saber circuit function modeling and simulation; 2, determining the failure mode of a device to be simulated; 3, modeling the failure; 4, injecting the failure; 5, simulating a failed circuit to generate a failure simulation result; 6, setting a failure criterion; and 7, giving a failure analyzing result. Regarding the problem that the conventional circuit failure simulation can be only used for digital circuits, the method provides a practical failure simulation method based on the digital-analog hybrid simulation platform Saber. Furthermore, many failure simulation models which cannot be solved by predecessors are added, and 48 failure modes can be simulated. Realization of automatic failure injection greatly improves the failure simulation efficiency. The direct interface between Saber and failure simulation is broken through,and an effective signal failure determination method is provided.

The invention relates to the technical field of radar circuit fault detection and diagnosis, specifically to a radar signal unit performance test and fault diagnosis system based on a general test platform. The system comprises a general test platform, a test procedure set, an interface connection module, an interface test adapter and a signal processing unit to be tested, the general test platform includes general test instruments and hardware resources including a test procedure set, a programmable power supply, a spectrometer, a signal generator, a digital oscilloscope, a digital triple-purpose meter, a digital I/O, a communication interface, a multichannel ADC and a multichannel DAC, and the test platform is connected with the interface test adapter through the interface connection module. By adoption of a system architecture of the general test platform plus the interface test adapter, the system has very strong universality and expandability, allows multiple equipment to share one test platform, and the interface test adapter adopts a hardware architecture of FPGA+ARM, and has very strong universality, expansibility and reconfigurability.

An object of the present invention is to provide a semiconductor device capable of recognizing circuit malfunction in an actual operation and of specifying a point of the circuit malfunction, and the semiconductor device, which does not induce the malfunction in the circuit of a subsequent stage when restoring the malfunction. The present invention is the semiconductor device provided with a plurality of logic circuits and a plurality of judging circuits for judging malfunction based on data from the logic circuits, wherein each of the judging circuits is provided with a first register, delay unit, a second register, a comparator and scanning unit, which makes the second register a shift register to allow to transmit an error signal held in the second register to the subsequent stage, while allowing the comparator to hold a comparison result.

To detect accurately an insulation fault in a load circuit, Power supply lines and an electric heater (a load circuit) are connected by a detecting portion to detect a detected voltage (detected value) in accordance with the magnitude of a leakage current Id that flows through a ground between the power supply lines and the electric heater, and an evaluation as to whether or not there is a breakdown of insulation of the electric heater relative to the ground is performed by an evaluating portion based on the detected value obtained when the relay contact points are open.

A method for predicting the failure of a data storage device having a slider heater is disclosed. For slider heaters exhibiting a decreasing resistance aging characteristic, a failure warning is produced when heater resistance suddenly increases 2 to 5%, or dR/dt changes sign from negative to positive. For slider heaters exhibiting an increasing resistance aging characteristic, a failure warning is produced when the heater resistance suddenly drops 2 to 5%, or dR/dt changes sign from positive to negative. Additionally, random changes in heater resistance exceeding nominal measurement error may also be utilized to produce a failure warning. This method provides advance warning of potential data read/write errors well before the open circuit failure of the slider heater occurs.

The invention discloses a probabilistic neural network-based tolerance-circuit fault diagnosis method, which comprises the following steps of: selecting a pulse signal source as the energization of a fault circuit to be detected; carrying out Monte Carlo analysis on the fault circuit so as to obtain an amplitude-frequency response signal of the fault circuit to be detected; carrying out three-layer wavelet packet decomposition on the amplitude-frequency response signal of the fault circuit so as to obtain low and high frequency coefficients of the amplitude-frequency response signal, carryingout threshold quantification on the wavelet packet decomposition coefficients, then carrying out wavelet packet reconstruction according to the lowest-layer low frequency wavelet packet decompositioncoefficients and the high frequency wavelet packet decomposition coefficients subjected to threshold quantification so as to complete the de-noising processing of the wavelet packet; calculating the band-gap energy of the response signal according to the low and high coefficients obtained after wavelet packet reconstruction, and constituting a fault characteristic vector by using the band-gap energy; and inputting the fault characteristic vector in a fault grader of the probabilistic neural network to realize circuit fault diagnosis. The method has the advantages of high right fault diagnosisrate, simple structure, short training time, high fault tolerance and strong extrapolation ability.

The invention provides a method for measuring the distance between two ends based on real-time circuit parameter measurement. The method comprises the following steps: 1) when a power transmission circuit has a failure, a data collection device synchronously samples voltage and current signals of two ends of the circuit, and completes alignment of sampled data on two sides of the power transmission circuit; 2) the voltage and current values before the circuit has the failure are substituted into a parametric equation to acquire real-time circuit parameters; and 3) the real-time circuit parameters and the voltage and current values at the failure moment are substituted into a dual-end voltage linear distributional equation to acquire the distance from the transmission circuit failure pointto a reference point. By utilizing the method, the distance measurement accuracy is high, and is not influenced by the environment surrounding the circuit, weather and other factors, so that distancemeasurement errors caused by inaccurate circuit parameters are avoided. By searching the rule of voltage linear distributed equation, a dual-end distance measurement equation can be quickly solved with small calculated amount, and non-convergent result or false root which possibly exists in the conventional solving method cannot occur. In the method, the launched data collection device is utilized, but a new device is not required.

The invention discloses a DC-DC converter health monitoring and fault prediction method based on multiple SVDD models. Firstly, a state signal (input voltage, input current, output voltage and output current) of a health DC-DC converter is acquired, and multi-group performance parameters (an output voltage average value Uo, an output ripple voltage Upp and efficiency Eta) are calculated; then three training sample sets are constructed, and three SVDD models of a circuit under the health state are acquired; after a health reference value of the circuit is calculated, the DC-DC converter to be tested is monitored, relative distance of all the performance parameters (Uo, Upp and Eta) to the corresponding SVDD models is calculated and summation is performed in a weighting way so that a circuit fault characteristic parameter Hk is acquired; and the Hk is compared with the reference value, and when Hk is less than the reference value, the circuit is in the abnormal state, and thus fault prediction is performed on the circuit by adopting a Gauss process model. Variation situations of the multiple performance parameters of the DC-DC converter are comprehensively considered so that defects of single information are compensated, the fault characteristic parameter capable of comprehensively assessing the performance state of the circuit is acquired and accurate fault prediction of the circuit can be effectively realized.

Defects in components in ICs which may cause circuit failures during operation of the IC are often difficult to detect during and immediately after fabrication of the IC by DC test methods. A method of testing components to detect such defects using AC Impedance Spectroscopy is disclosed. Data may be analyzed using Nyquist plots and Bode plots. Nyquist plots of typical defect types are disclosed. Components may include MOS transistor gate structures, contacts, vias and metal interconnect lines. Components tested may be contained in integrated circuits or in test circuits. Integrated circuits containing components tested by AC Impedance Spectroscopy may be partially fabricated or deprocessed after fabrication.