Zero-power sampling sar adc circuit and method

Abstract

A switched-capacitor circuit (10, 32 or 32A) samples a first signal (VIN+) onto a first capacitor (C1 or CIN1) by switching a top plate thereof via a summing conductor (13) to a first reference voltage (VSS) and switching a bottom plate thereof to the first signal. A second signal (VIN-) is sampled onto a second capacitor (C3 or CIN3) by switching a top plate thereof to the second signal and switching a bottom plate thereof to the first reference voltage. After the sampling, the top plate of the second capacitor is coupled to the top plate of the first capacitor. The bottom plate of the second capacitor is coupled to the first reference voltage.; The bottom plate of the first capacitor is coupled to a second reference voltage (VDD or VREF), to thereby cancel at least a portion of a common mode input voltage component from the first conductor (13), hold the sampled differential charge on the summing conductor and establish a predetermined common mode voltage thereon, and prevent the summing conductor from having a voltage which allows the leakage of charge therefrom. The switched-capacitor circuit may be a SAR, an integrator, or an amplifier.

Description

technical field [0001] The present invention relates generally to switched capacitor circuits including SAR ADCs (Successive Approximation Register Analog-to-Digital Converters), and more particularly to improved techniques for avoiding charge leakage through integrated circuit substrate diodes caused by switched capacitor circuits, SAR The analog summing node voltage swing outside the acceptable range in the ADC is caused, and the present invention still more particularly relates to a SAR ADC that is simpler and cheaper than those available in the prior art. Background technique [0002] PRIOR ART FIG. 1A is a simplified diagram of a basic well-known single-ended SAR ADC that implements a conventional SAR algorithm to convert an analog input voltage VIN into a digital output signal DOUT. See, for example, Figures 13.5, 13.6, and 13.7, and the associated text in David Johns and Ken Martin, "Analog Integrated Circuit Design" (1997 John Wiley & Sons, Inc.). [0003] The SAR A...

AI Technical Summary

Problems solved by technology

In the prior art SAR ADC 300 in FIG. 1B , this causes redistributed charge from the CDAC capacitor to leak through to discharge through the substrate diode associated with the top plate switch, thereby causing conversion errors

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