20results about "Threshold modification in field effect transistors" patented technology

The application provides a potential generating circuit, an inverter, a delay circuit and a logic gate circuit. The potential generating circuit comprises a first transistor and a second transistor, a potential of a substrate end of the first transistor changes with a first parameter, the first parameter being any one of a supply voltage, an operating temperature and a manufacturing process of the potential generating circuit, wherein a gate end of the first transistor is connected to a drain end of the first transistor, the substrate end of the first transistor serving as an output end of the potential generating circuit, and a gate end of the second transistor is connected to a drain end of the second transistor. Thus, the substrate end of the first transistor can output a potential which changes with any one of the supply voltage, the operating temperature and the manufacturing process.

Systems and methods related to low power cryo-CMOS circuits with non-volatile threshold voltage offset compensation are provided. A system (400) for interfacing with qubit gates comprises a first plurality of devices (420) configured to operate in a cryogenic environment; a second plurality of devices (430), different from the first plurality of devices (420), configured to operate in the cryogenic environment; and control logic (450). The control logic (450) is coupled to each of the first plurality of devices (420) and the second plurality of devices (430), and is configured to modify a threshold voltage associated with each of the first plurality of devices (420) and the second plurality of devices (430) such that a first threshold voltage associated with each of the first plurality of devices (420) is different from a second threshold voltage associated with each of the second plurality of devices (430).

A power gating circuit including: a power gating transistor; a gate bias generating circuit configured to provide a gate bias control signal to the gate of the power gating transistor; and a body bias generating circuit configured to provide a body bias control signal to the body of the power gating transistor, wherein when the power gating transistor is turned on, the gate bias generating circuit provides the gate bias control signal having a positive voltage level and the body bias generating circuit provides the body bias control signal having the positive voltage level, and when the power gating transistor is turned off, the gate bias generating circuit provides the gate bias control signal having a ground voltage level or a negative voltage level, and the body bias generating circuit provides the body bias control signal having the ground voltage level or the negative voltage level.

The circuit device includes an output terminal, an output transistor, and a gate voltage control circuit. The output transistor is disposed between the first power supply node and the output terminal. After the input signal (TX) transitions from a first logic level to a second logic level, the gate voltage control circuit causes the gate voltage of the output transistor to change at a first time-voltage change rate. After the gate voltage reaches a first determination voltage, the circuit causes the gate voltage to change at a second time-voltage change rate that is smaller than the first time-voltage change rate. After the gate voltage reaches a second determination voltage, the circuit causes the gate voltage to change at a third time-voltage change rate that is larger than the second time-voltage change rate.

Systems and methods related to low power cryo-CMOS circuits with non-volatile threshold voltage offset compensation are provided. A system (700) includes a plurality of devices (760) configured to operate in a cryogenic environment (<300 K), where a first distribution of a threshold voltage associated with the plurality of devices (760) has a first value indicative of a measure of spread of the threshold voltage. The system (700) further includes control logic (712, 714), coupled to each of the plurality of devices (760), configured to modify (714out) a threshold voltage associated with each of the plurality of devices (760) such that the first distribution is changed to a second distribution having a second value of the measure of spread of the threshold voltage representing a lower variation among threshold voltages of the plurality of devices.

A breakdown-voltage control circuit includes a high voltage monitor circuit and a first voltage switching circuit 1112 connected to the high voltage monitor circuit, the high voltage monitor circuit generating a first reference signal based on an input signal inputted to the high voltage monitor circuit, the first voltage switching circuit comparing a first application voltage applied to the first voltage switching circuit with the first reference signal, outputting the first reference signal as a first control signal when the first application voltage is exceeded, and outputting the first application voltage as the first control signal when the voltage of the first reference signal is less than the first application voltage.

A circuit for implementing ring oscillator synchronous chopping is described herein. The circuit may include a pair of differently arranged ring oscillators, chopping logic, and control logic. The chopping logic is configured to perform a chopping operation of the ring oscillator. The control logic is configured to: stop each ring oscillator in a predefined state; after the two ring oscillators are stopped, chopping logic is started to execute chopping operation; and restarting the two ring oscillators after the chopping operation is completed.

According to an aspect, there is provided a swing-boosted differential oscillator (500) and a method for trimming the oscillator. The oscillator comprises a switch (110′) for connecting a set of capacitors (C1, C2) alternately to power supply and ground (102′, 112′) based on a switching control (116A′, 116B′), two comparators (502, 504) configured to produce an output signal of the oscillator (ck) and the switching control (116A′, 116B′) via a multiplexer (508) by comparing a voltage of the capacitors (C1, C2) at the inputs (VC1, VC2) of the comparators to a threshold voltage (VBB), where the comparators comprising back gate bias input (FIG. 5: 804, FIG. 8: Vbb, 804) for controlling the threshold voltage of the comparators, the threshold voltage trimming the frequency of the output signal of the oscillator.

An integrated circuit includes an asymmetry upper threshold circuit outputting an upper-branch enabling signal, an asymmetry lower threshold circuit outputting a lower-branch enabling signal, and a control circuit which changes an output voltage when the logic levels of the upper-branch enabling signal and the lower-branch enabling signal are changed consecutively. The upper-branch enabling signal is set to a first upper-branch logic level when an input voltage received by the integrated circuit rises across a main upper threshold, and to a second upper-branch logic level when the input voltage falls across a supplementary upper threshold which is higher than the main upper threshold. The lower-branch enabling signal is set to a first lower-branch logic level when the input voltage falls across a main lower threshold, and to a second lower-branch logic level when the input voltage rises across a supplementary lower threshold which is lower than the main lower threshold.

Described herein is a circuitry for enabling synchronized chopping for ring oscillators. The circuitry may include a differentially arranged pair of ring oscillators; a chopping logic configured to perform a chopping operation for the ring oscillators; and a control logic configured to: stop each ring oscillator in a predefined state; enable the chopping logic to perform the chopping operation after both ring oscillators are stopped; and restart both ring oscillators after the chopping operation is completed.

A multiplexer includes first and second selection circuits and a leakage current control circuit. The first selection circuit is selectively turned on according to a first selection signal to transmit a first input signal to an output node to generate an output voltage. The second selection circuit includes first and second switches. The first switch is selectively turned on according to a second selection signal, and the second switch is turned on according to first and second control signals to transmit a second input signal to the output node when the first switch is turned on. The leakage current control circuit compares the output voltage with a plurality of reference voltages to generate a plurality of detection signals when the first selection circuit is turned on, and selectively adjusts a level of the first or the second control signal according to the detection signals and the second selection signal.

An interface circuit, a method for controlling the interface circuit, a chip, and a terminal device are provided. The interface circuit includes a first PMOS transistor, an input signal control circuit, a bias circuit, a signal input end, and an input / output end. The bias circuit includes a substrate bias voltage generation end and a bias voltage generation end. The bias circuit is coupled to a high-level power supply end, the input / output end, and a ground end. The input signal control circuit is connected to the signal input end, the bias voltage generation end, and a gate of the first PMOS transistor; a first electrode of the first PMOS transistor is connected to the high-level power supply end, and a second electrode of the first PMOS transistor is connected to the input / output end.

A device with inverter functionality and a tunable trigger voltage includes a PFET and an NFET connected in series. The FETs are multi-gated and at least one FET is a threshold voltage (VT) programmable FET. In some embodiments, both FETs are dual-gated (i.e., have two gates) with at least one gate of the two gates being programmable (i.e., configured for VT programmability). In these embodiments, the device includes an input node connected to primary gates of the FETs and additional nodes connected to VT-programmable secondary gates of the FETs, respectively. Alternatively, the device includes an input node connected to secondary gates of the FETs and additional nodes connected to VT-programmable primary gates of the FETs, respectively. Alternatively, the device includes an input node connected to primary gates of the FETs and another input node connected to secondary gates of the FETs, where the primary gates and / or secondary gates are programmable.

An apparatus, such as a clock signal receiver circuit, is disclosed. The apparatus includes a common mode voltage generator configured to generate a common mode voltage at an output; an input circuit comprising: a first field effect transistor (FET); a second FET; a first capacitor coupled between a first differential clock input and a first gate of the first FET; a second capacitor coupled between a second differential clock input and a second gate of the second FET; a first resistive device coupled between the output of the common mode voltage generator and the first gate of the first FET; and a second resistive device coupled between the output of the common mode voltage generator and the second gate of the second FET; and an active inductance circuit coupled in series with the first and second FETs between an upper voltage rail and a lower voltage rail, respectively.

This invention provides an integrated circuit with a variable threshold circuit. The integrated circuit includes: an asymmetric upper threshold circuit that outputs an upper branch enable signal; an asymmetric lower threshold circuit that outputs a lower branch enable signal; and a control circuit that changes the output voltage when the logic levels of the upper and lower branch enable signals change continuously. The upper branch enable signal is set to a first upper branch logic level when the input voltage received by the integrated circuit rises above a main upper threshold and is set to a second upper branch logic level when the input voltage falls below an auxiliary upper threshold, wherein the auxiliary upper threshold is higher than the main upper threshold. The lower branch enable signal is set to a first lower branch logic level when the input voltage falls below a main lower threshold and is set to a second lower branch logic level when the input voltage rises above an auxiliary lower threshold, wherein the auxiliary lower threshold is lower than the main lower threshold.

Reduced delay and improved threshold tracking over PVT in a comparator input circuit and comparator are provided by circuits that include an inverter stage having a first complementary pair of transistors connected in a push-pull configuration. An input of the inverter stage is coupled to the gates of the first complementary pair of transistors, and an output of the inverter is coupled to the drains of the first complementary pair of transistors. The circuits also include one or more first degeneration transistors coupled between a source of one of the first complementary pair of transistors and a power supply rail of the circuit, and a reference circuit with an output coupled to one or more gates of the first degeneration transistors. The reference circuit controls the one or more first degeneration transistors to cause the inverter stage to have a threshold voltage equal to a threshold control voltage.

The application relates to the technical field of radio frequency switches, and discloses a positive and negative level conversion circuit. The positive and negative level conversion circuit drives a positive voltage power input unit and a negative voltage power input unit through a first logic signal and a second logic signal, forms a first conversion signal with positive voltage and zero voltage alternately at a first output unit, and forms a second conversion signal with zero voltage and negative voltage alternately at a second output unit through a positive voltage inverter ring, a complementary logic circuit, a first switch, a second switch, a third switch, a fourth switch and a negative voltage inverter ring, so that the first output unit alternately works in a positive voltage domain and a ground voltage domain, and the second output unit alternately works in a negative voltage domain and the ground voltage domain. At this time, four layers of switches coexist on a current path, the risk that the switches bear 2 times of positive voltage is avoided, and the technical problem that the switches of the positive and negative level conversion circuit in the prior art have the risk of overvoltage is solved.

The present application provides a drive circuit and a semiconductor device. Even if the potential applied to a low potential terminal varies, the drive circuit can be protected. A drive circuit is provided, which controls an output section that switches whether to supply a current to an output line in accordance with a potential difference between a first control signal input and a voltage of the output line, wherein the drive circuit includes: a control line that transmits the first control signal to the output section; a low potential line to which a predetermined reference potential is applied; a first connection switching section that switches whether to connect the control line and the low potential line in accordance with a second control signal; and a cutoff section that is provided in series with the first connection switching section between the control line and the low potential line, and cuts off the control line and the low potential line based on a potential of the low potential line.

A device with inverter functionality and a tunable trigger voltage includes a PFET and an NFET connected in series. The FETs are multi-gated and at least one FET is a threshold voltage (VT) programmable FET. In some embodiments, both FETs are dual-gated (i.e., have two gates) with at least one gate of the two gates being programmable (i.e., configured for VT programmability). In these embodiments, the device includes an input node connected to primary gates of the FETs and additional nodes connected to VT-programmable secondary gates of the FETs, respectively. Alternatively, the device includes an input node connected to secondary gates of the FETs and additional nodes connected to VT-programmable primary gates of the FETs, respectively. Alternatively, the device includes an input node connected to primary gates of the FETs and another input node connected to secondary gates of the FETs, where the primary gates and / or secondary gates are programmable.

Disclosed in an interface circuit, in which: a current input circuit receives an input current signal of a signal input terminal, an input voltage detection circuit compares an input voltage signal of the signal input terminal with a reference voltage, and provides a detection signal to the current input circuit according to the comparison result, a phase-inversion output circuit is connected with the current input circuit at the first node, and generates a voltage conversion signal according to a voltage potential of the first node, and a buffer circuit performs signal shaping on the voltage conversion signal to obtain an output signal. The current input circuit pulls up the voltage potential of the first node when the detection signal indicates that the input voltage signal is greater than the reference voltage and the input current signal is greater than a reference current.