47results about "Threshold modification in field effect transistors" patented technology

An apparatus and configuring scheme where a capacitive input circuit can be programmed to perform different logic functions by adjusting the switching threshold of the capacitive input circuit. Digital inputs are received by respective capacitors on first terminals of those capacitors. The second terminals of the capacitors are connected to a summing node. A pull-up and pull-down device are coupled to the summing node. The pull-up and pull-down devices are controlled separately. During a reset phase, the pull-up and / or pull-down devices are turned on or off in a sequence, and inputs to the capacitors are set to condition the voltage on node n1. As such, a threshold for the capacitive input circuit is set. After the reset phase, an evaluation phase follows. In the evaluation phase, the output of the capacitive input circuit is determined based on the inputs and the logic function configured during the reset phase.

The present application provides a potential generating circuit, an inverter, a delay circuit and a logic gate circuit. The potential generating circuit includes: a first transistor and a second transistor, the potential of the substrate end of the first transistor changes with the change of a first parameter, the first parameter is any one of the power supply voltage, the operating temperature and the manufacturing process of the potential generating circuit, and the potential of the substrate end of the second transistor changes with the change of the first parameter. Among them, the gate end of the first transistor is connected to the drain end of the first transistor, the substrate end of the first transistor serves as the first output end of the potential generating circuit, the gate end of the second transistor is connected to the drain end of the second transistor, and the substrate end of the second transistor serves as the second output end of the potential generating circuit. Thus, the first output end and the second output end can respectively output a potential that changes with any one of the power supply voltage, the operating temperature and the manufacturing process.

The application provides a potential generating circuit, an inverter, a delay circuit and a logic gate circuit. The potential generating circuit comprises a first transistor and a second transistor, a potential of a substrate end of the first transistor changes with a first parameter, the first parameter being any one of a supply voltage, an operating temperature and a manufacturing process of the potential generating circuit, wherein a gate end of the first transistor is connected to a drain end of the first transistor, the substrate end of the first transistor serving as an output end of the potential generating circuit, and a gate end of the second transistor is connected to a drain end of the second transistor. Thus, the substrate end of the first transistor can output a potential which changes with any one of the supply voltage, the operating temperature and the manufacturing process.

Systems and methods related to low power cryo-CMOS circuits with non-volatile threshold voltage offset compensation are provided. A system (400) for interfacing with qubit gates comprises a first plurality of devices (420) configured to operate in a cryogenic environment; a second plurality of devices (430), different from the first plurality of devices (420), configured to operate in the cryogenic environment; and control logic (450). The control logic (450) is coupled to each of the first plurality of devices (420) and the second plurality of devices (430), and is configured to modify a threshold voltage associated with each of the first plurality of devices (420) and the second plurality of devices (430) such that a first threshold voltage associated with each of the first plurality of devices (420) is different from a second threshold voltage associated with each of the second plurality of devices (430).

An output driver and an output buffer circuit including the same, the output driver including: a driving circuit electrically connected to a pad and including at least two transistors connected in series with each other; and an anti-leakage circuit, wherein the anti-leakage circuit is configured to block the leakage current of the driving circuit. The gates of the at least two transistors are electrically connected to each other, and the leakage prevention circuit is configured to control a voltage level of an intermediate node between the at least two transistors based on a signal level of the pad.

To provide systems and methods relating to low power cryo-CMOS circuits with non-volatile threshold voltage offset compensation.SOLUTION: A system includes a plurality of devices configured to operate in a cryogenic environment, and a first distribution of a threshold voltage associated with the plurality of devices has a first value indicative of a measure of spread of the threshold voltage. The system further includes control logic coupled to each of the plurality of devices. The control logic is configured to modify a threshold voltage associated with each of the plurality of devices such that the first distribution is changed to a second distribution having a second value of the measure of spread of the threshold voltage, the second value representing a lower variation among threshold voltages of the plurality of devices.SELECTED DRAWING: Figure 6

A power gating circuit including: a power gating transistor; a gate bias generating circuit configured to provide a gate bias control signal to the gate of the power gating transistor; and a body bias generating circuit configured to provide a body bias control signal to the body of the power gating transistor, wherein when the power gating transistor is turned on, the gate bias generating circuit provides the gate bias control signal having a positive voltage level and the body bias generating circuit provides the body bias control signal having the positive voltage level, and when the power gating transistor is turned off, the gate bias generating circuit provides the gate bias control signal having a ground voltage level or a negative voltage level, and the body bias generating circuit provides the body bias control signal having the ground voltage level or the negative voltage level.

The circuit device includes an output terminal, an output transistor, and a gate voltage control circuit. The output transistor is disposed between the first power supply node and the output terminal. After the input signal (TX) transitions from a first logic level to a second logic level, the gate voltage control circuit causes the gate voltage of the output transistor to change at a first time-voltage change rate. After the gate voltage reaches a first determination voltage, the circuit causes the gate voltage to change at a second time-voltage change rate that is smaller than the first time-voltage change rate. After the gate voltage reaches a second determination voltage, the circuit causes the gate voltage to change at a third time-voltage change rate that is larger than the second time-voltage change rate.

Reduced delay and improved threshold tracking over PVT in a comparator input circuit and comparator are provided by circuits that include an inverter stage having a first complementary pair of transistors connected in a push-pull configuration. An input of the inverter stage is coupled to the gates of the first complementary pair of transistors, and an output of the inverter is coupled to the drains of the first complementary pair of transistors. The circuits also include one or more first degeneration transistors coupled between a source of one of the first complementary pair of transistors and a power supply rail of the circuit, and a reference circuit with an output coupled to one or more gates of the first degeneration transistors. The reference circuit controls the one or more first degeneration transistors to cause the inverter stage to have a threshold voltage equal to a threshold control voltage.

The invention discloses a reinforced circuit for SiC MOSFET space application. The reinforced circuit comprises an MOSFET device Q1, an MOSFET device Q2, a resistor R1, a high-voltage power supply, a first driver and a second driver, wherein the source electrode of the MOSFET device Q1 is connected with the drain electrode of the MOSFET device Q2; the drain electrode of the MOSFET device Q1 is connected with one end of the resistor R1, and one end of the resistor R1 is connected with the positive electrode of the high-voltage power supply; the source electrode of the MOSFET device Q2 and the negative electrode of the high-voltage power supply are connected and then are grounded together; the output end of the first driver is connected with the grid electrode of the MOSFET device Q1, and the reference end of the first driver is connected with the source electrode of the MOSFET device Q1; the output end of the second driver is connected with the grid electrode of the MOSFET device Q2, and the reference end of the second driver is connected with the source electrode of the MOSFET device Q2; the first driver and the second driver are connected with a square wave input signal. According to the invention, the single event effect resistance of the device in a space radiation environment is enhanced, and the overall reliability of the device is improved.

According to one aspect, there is provided a swing-enhanced differential oscillator (500) and a method for trimming an oscillator. The oscillator comprises: a switch (110 ') for alternately connecting a set of capacitors (C1, C2) to a power supply and ground (102', 112 ') based on a switching control (116A', 116B '); two comparators (502, 504) configured to be coupled to each other by coupling capacitors (C1, C2) at inputs (VC1, VC2) of the comparators (502, 504) to the capacitors (C1, C2); an output signal (ck) of the oscillator and a switching control (116A ', 116B') are generated via a multiplexer (508) by comparing a voltage of the oscillator (C1, C2) with a threshold voltage (VBB), where the comparator includes a back gate bias input (Figure 5: 804, Figure 8: Vbb, 804) for controlling the threshold voltage of the comparator that trims the frequency of the output signal of the oscillator.

A device with inverter functionality and a tunable trigger voltage includes a PFET and an NFET connected in series. The FETs are multi-gated and at least one FET is a threshold voltage (VT) programmable FET. In some embodiments, both FETs are dual-gated (i.e., have two gates) with at least one gate of the two gates being programmable (i.e., configured for VT programmability). In these embodiments, the device includes an input node connected to primary gates of the FETs and additional nodes connected to VT-programmable secondary gates of the FETs, respectively. Alternatively, the device includes an input node connected to secondary gates of the FETs and additional nodes connected to VT-programmable primary gates of the FETs, respectively. Alternatively, the device includes an input node connected to primary gates of the FETs and another input node connected to secondary gates of the FETs, where the primary gates and / or secondary gates are programmable.

A high-low level conversion circuit with a wide threshold value relates to the technical field of integrated circuits, and is mainly structurally characterized in that the drain end of a twelfth PMOS (P-channel Metal Oxide Semiconductor) tube is connected with the drain end of a ninth NMOS (N-channel Metal Oxide Semiconductor) tube through a first resistor and a second resistor which are connected in series; the connection point of the first resistor and the second resistor serves as a first reference point A to be connected with input voltage VIN. The source end of the ninth NMOS tube is connected with the source end of the fourth PMOS tube; the drain end of the fourth PMOS tube is connected with the drain end of the fifth NMOS tube to serve as a fourth reference point D; the drain end of the fifth NMOS tube is sequentially connected with the first phase inverter and the second phase inverter; when the potential of the point A is reduced to be near VE + VTH4 under the driving of a VIN end, the fourth PMOS tube enters a saturation region, a small fluctuation of the level of the point A causes a huge change of the level of the point D, and the level of the point D enters a level overturning threshold value of a post-stage inverter more quickly. According to the invention, the conversion of high and low voltage control signals is realized, the flip voltage is accurately controlled, the high and low level threshold values are increased, and the punch-through current during level flip is reduced.

Systems and methods related to low power cryo-CMOS circuits with non-volatile threshold voltage offset compensation are provided. A system (700) includes a plurality of devices (760) configured to operate in a cryogenic environment (<300 K), where a first distribution of a threshold voltage associated with the plurality of devices (760) has a first value indicative of a measure of spread of the threshold voltage. The system (700) further includes control logic (712, 714), coupled to each of the plurality of devices (760), configured to modify (714out) a threshold voltage associated with each of the plurality of devices (760) such that the first distribution is changed to a second distribution having a second value of the measure of spread of the threshold voltage representing a lower variation among threshold voltages of the plurality of devices.

The invention relates to a device with inverter function and adjustable trigger voltage. A device having an inverter function and an adjustable trigger voltage includes a PFET and an NFET connected in series. The FETs are multi-gate, and at least one FET is a threshold voltage (VT) programmable FET. In some embodiments, both FETs are bigate (i.e., having two gates), where at least one of the two gates is programmable (i.e., configured for VT programmability). In these embodiments, the device includes an input node connected to a primary gate of the FET and an additional node connected to a VT programmable secondary gate of the FET, respectively. Alternatively, the device includes an input node connected to a secondary gate of the FET and an additional node connected to a VT programmable main gate of the FET, respectively. Alternatively, the device includes an input node connected to the primary gate of the FET and another input node connected to the secondary gate of the FET, where the primary gate and / or the secondary gate are programmable.

An integrated circuit includes an asymmetry upper threshold circuit outputting an upper-branch enabling signal, an asymmetry lower threshold circuit outputting a lower-branch enabling signal, and a control circuit which changes an output voltage when the logic levels of the upper-branch enabling signal and the lower-branch enabling signal are changed consecutively. The upper-branch enabling signal is set to a first upper-branch logic level when an input voltage received by the integrated circuit rises across a main upper threshold, and to a second upper-branch logic level when the input voltage falls across a supplementary upper threshold which is higher than the main upper threshold. The lower-branch enabling signal is set to a first lower-branch logic level when the input voltage falls across a main lower threshold, and to a second lower-branch logic level when the input voltage rises across a supplementary lower threshold which is lower than the main lower threshold.

A breakdown-voltage control circuit includes a high voltage monitor circuit and a first voltage switching circuit 1112 connected to the high voltage monitor circuit, the high voltage monitor circuit generating a first reference signal based on an input signal inputted to the high voltage monitor circuit, the first voltage switching circuit comparing a first application voltage applied to the first voltage switching circuit with the first reference signal, outputting the first reference signal as a first control signal when the first application voltage is exceeded, and outputting the first application voltage as the first control signal when the voltage of the first reference signal is less than the first application voltage.

A circuit for implementing ring oscillator synchronous chopping is described herein. The circuit may include a pair of differently arranged ring oscillators, chopping logic, and control logic. The chopping logic is configured to perform a chopping operation of the ring oscillator. The control logic is configured to: stop each ring oscillator in a predefined state; after the two ring oscillators are stopped, chopping logic is started to execute chopping operation; and restarting the two ring oscillators after the chopping operation is completed.

According to an aspect, there is provided a swing-boosted differential oscillator (500) and a method for trimming the oscillator. The oscillator comprises a switch (110′) for connecting a set of capacitors (C1, C2) alternately to power supply and ground (102′, 112′) based on a switching control (116A′, 116B′), two comparators (502, 504) configured to produce an output signal of the oscillator (ck) and the switching control (116A′, 116B′) via a multiplexer (508) by comparing a voltage of the capacitors (C1, C2) at the inputs (VC1, VC2) of the comparators to a threshold voltage (VBB), where the comparators comprising back gate bias input (FIG. 5: 804, FIG. 8: Vbb, 804) for controlling the threshold voltage of the comparators, the threshold voltage trimming the frequency of the output signal of the oscillator.

The invention discloses a multiplexer and a leakage current control method thereof, and relates to the technical field of multiplexers. The multiplexer comprises a first selection circuit, a second selection circuit and a leakage current control circuit. The first selection circuit is selectively conducted according to the first selection signal so as to transmit a first input signal to an output node to generate an output voltage. The second selection circuit comprises a first switch and a second switch. The first switch is selectively turned on according to a second selection signal, and the second switch is turned on according to the first and second control signals so as to transmit a second input signal to the output node when the first switch is turned on. The leakage current control circuit compares the output voltage with a plurality of reference voltages to generate a plurality of detection signals when the first selection circuit is turned on, and selectively adjusts the level of the first control signal or the second control signal according to the plurality of detection signals and the second selection signal.

An output driver includes a driving circuit electrically connected to a pad and including at least two transistors connected to each other in series, and a leakage prevention circuit configured to block a leakage current of the driving circuit. Gates of the at least two transistors are electrically connected to each other, and the leakage prevention circuit is configured to control a voltage level of an intermediate node between the at least two transistors based on a signal level of the pad.

Certain aspects of the present disclosure provide a circuit that connects an output of a voltage reference circuit powered by a relatively high voltage to an input of a voltage buffer that is configured to generate a voltage lower than the high voltage. The connection circuit prevents the high voltage from reaching the input of the voltage buffer. An example electronic circuit generally includes: a voltage reference circuit configured to be powered by a relatively high voltage, a buffer circuit configured to generate a relatively low voltage compared to the relatively high voltage, and a circuit coupled between the output of the voltage reference circuit and the input of the buffer circuit, the circuit configured to prevent the higher voltage from reaching the input of the buffer circuit.

A pass-gate gate driver control system is presented that includes a gate driver control (110) and a pass-gate switch (106, 108). The pass gate switch includes a P-channel metal oxide semiconductor (PMOS) transistor and an N-channel metal oxide semiconductor (NMOS) transistor. The gate driver control includes a through-gate charge injector (112) arranged to vary a charging speed and / or a discharging speed of charge at the gate of the PMOS transistor and / or the NMOS transistor.

An integrated circuit includes an asymmetry upper threshold circuit outputting an upper-branch enabling signal, an asymmetry lower threshold circuit outputting a lower-branch enabling signal, and a control circuit which changes an output voltage when the logic levels of the upper-branch enabling signal and the lower-branch enabling signal are changed consecutively. The upper-branch enabling signal is set to a first upper-branch logic level when an input voltage received by the integrated circuit rises across a main upper threshold, and to a second upper-branch logic level when the input voltage falls across a supplementary upper threshold which is higher than the main upper threshold. The lower-branch enabling signal is set to a first lower-branch logic level when the input voltage falls across a main lower threshold, and to a second lower-branch logic level when the input voltage rises across a supplementary lower threshold which is lower than the main lower threshold.

Described herein is a circuitry for enabling synchronized chopping for ring oscillators. The circuitry may include a differentially arranged pair of ring oscillators; a chopping logic configured to perform a chopping operation for the ring oscillators; and a control logic configured to: stop each ring oscillator in a predefined state; enable the chopping logic to perform the chopping operation after both ring oscillators are stopped; and restart both ring oscillators after the chopping operation is completed.

A system and method relating to a low-power cryo-CMOS circuit with non-volatile threshold voltage offset compensation is provided. The system includes a plurality of devices configured to operate in a cryogenic environment, wherein a first distribution of threshold voltages of the plurality of devices has a first value representing a measure of threshold voltage spread. The system further includes control logic coupled to each of the plurality of devices, the control logic configured to change the threshold voltage of each of the plurality of devices such that the first distribution is changed to a second distribution having a second value representing a lower variation between the threshold voltages of the plurality of devices.

A multiplexer includes first and second selection circuits and a leakage current control circuit. The first selection circuit is selectively turned on according to a first selection signal to transmit a first input signal to an output node to generate an output voltage. The second selection circuit includes first and second switches. The first switch is selectively turned on according to a second selection signal, and the second switch is turned on according to first and second control signals to transmit a second input signal to the output node when the first switch is turned on. The leakage current control circuit compares the output voltage with a plurality of reference voltages to generate a plurality of detection signals when the first selection circuit is turned on, and selectively adjusts a level of the first or the second control signal according to the detection signals and the second selection signal.

An interface circuit, a method for controlling the interface circuit, a chip, and a terminal device are provided. The interface circuit includes a first PMOS transistor, an input signal control circuit, a bias circuit, a signal input end, and an input / output end. The bias circuit includes a substrate bias voltage generation end and a bias voltage generation end. The bias circuit is coupled to a high-level power supply end, the input / output end, and a ground end. The input signal control circuit is connected to the signal input end, the bias voltage generation end, and a gate of the first PMOS transistor; a first electrode of the first PMOS transistor is connected to the high-level power supply end, and a second electrode of the first PMOS transistor is connected to the input / output end.

The present invention generally relates to a repeater for open-drain bus communication and a system comprising the same. More particularly, the present invention relates to a repeater that is suitable for I2C bus communication. A bus repeater (1) for open-drain bus communication is provided. The repeater (1) comprises at least one repeating unit, the repeating unit having an A-side terminal (2a) configured to be electrically connected to an A-side open-drain bus, and a B-side terminal (2b) configured to be electrically connected to a B-side open-drain bus. The repeater is operable in a first mode in which the repeating unit is configured to receive a signal at the A-side terminal (2a) and to produce a signal at the B-side terminal (2b) based on the signal received at the A-side terminal. The repeating unit comprises a B-side accelerator element (3b) electrically connected to the B-side terminal. Further, the repeating unit further comprises a first control unit (11a) configured to, when the repeating unit is operating in the first mode, control the B-side accelerator element (3b) to pull up a voltage at the B-side terminal (2b) when the voltage at the A-side terminal (2a) surpasses a first threshold voltage during a rising edge of said voltage, and to subsequently control the B-side accelerator element to stop pulling up the voltage at the B-side terminal when the voltage at the B-side terminal surpasses a second threshold voltage.

A device with inverter functionality and a tunable trigger voltage includes a PFET and an NFET connected in series. The FETs are multi-gated and at least one FET is a threshold voltage (VT) programmable FET. In some embodiments, both FETs are dual-gated (i.e., have two gates) with at least one gate of the two gates being programmable (i.e., configured for VT programmability). In these embodiments, the device includes an input node connected to primary gates of the FETs and additional nodes connected to VT-programmable secondary gates of the FETs, respectively. Alternatively, the device includes an input node connected to secondary gates of the FETs and additional nodes connected to VT-programmable primary gates of the FETs, respectively. Alternatively, the device includes an input node connected to primary gates of the FETs and another input node connected to secondary gates of the FETs, where the primary gates and / or secondary gates are programmable.