161 results about "Programming patterns" patented technology

Methods of programming a wordline of multi-level flash memory cells (MLB) having three or more data levels per bit corresponding to three or more threshold voltages are provided. The present invention employs an interactive program algorithm that programs the bits of the wordline of memory cells in two programming phases, comprising a rough programming phase and a fine programming phase to achieve highly compact Vt distributions. In one example, cell bit-pairs that are to be programmed to the same program pattern are selected along a wordline. Groups of sample bits are chosen for each wordline to represent each possible program level. The sample bits are then programmed to determine a corresponding drain voltage at which each sample group is first programmed. This fast-bit drain voltage (Fvd) for each program level essentially provides a wordline specific program characterization of the Vt required for the remaining bits of that wordline. In the rough programming phase, the bits of core cells are then programmed from a starting point that is relative to (e.g., slightly less than or equal to) the fast-bit Vd and according to a predetermined Vd and Vg profile of programming pulses. The bits of the complementary bit-pairs are alternately programmed in this way until the Vt of the bits attains a rough Vt level, which is offset lower than the final target threshold voltage level. Then in the second fine programming phase, the bits of the MLB cells of the wordline are further programmed with another predetermined Vd and Vg profile of programming pulses until the final target threshold voltage is achieved. The Vd and Vg profiles of programming pulses may further be tailored to accommodate the various bit-pair program pattern combinations possible. In this way, the bits of each wordline are fine-tune programmed to a data state to achieve a more precise Vt distribution, while compensating for the effects of complementary bit disturb.

An addressable lighting device and control system uses a user-actuable infrared or radio frequency operated remote control(s) to selectively or collectively generate an electronic address for the addressable lighting device on which the device will respond to all future signals from the remote control corresponding to that electronic address. The addressable lighting device has a programming mode for setting the address and a working mode for receiving control signals on the set address and correspondingly setting the desired intensity level of light. The addressable device may have the address set and changed locally (manually) or remotely using the remote control to switch modes, thereby avoiding the problems, expenses and mistakes associated with using dual in-line package (DIP) switches, binary, hex rotary switches, or thumbwheel switches normally used to set each one of the system's unit's unique address.

A method and apparatus for providing a simple user interface for programming scenes and multi-way groups in a home automation and control system is provided. Each device participating in the home automation and control system is equipped with control logic for providing the simple programming interface. Through the control logic, each device maintains its status in a system-wide programming mode and retains knowledge of its inclusion or exclusion in the current scene or multi-way group being programmed. When any device in the system receives indications that affect the system programming mode, such as a press on one of the buttons on the devices, the device broadcasts a notification message to all devices within the home automation and control system. The message maintains the integrity of the system programming mode. Each device knows when a scene or multi-way group being programmed is finally captured and the programming of a new scene or multi-way group has started.

In one aspect, a non-volatile memory device is provided which is operable in a programming mode and a read mode. The memory device includes a memory cell array which includes a plurality of non-volatile memory cells, a plurality of word lines, and a plurality of bit lines. The memory device further includes an internal data output line for outputting data read from the bit lines of the memory array, and a page buffer operatively connected between a bit line of the memory cell array and the internal data output line. The page buffer includes a sense node which is selectively connected to the bit line, a latch circuit having a latch node which is selectively connected to the sense node, a latch input path which sets a logic voltage of the latch node in the programming mode and the read mode, and a latch output path which is separate from the latch input path and which sets as logic voltage of the internal date output line according to the logic voltage of the latch node.

According to one aspect, a memory cell array includes a bit line connected to a plurality of nonvolatile memory cells, where the nonvolatile memory cells are selectively programmable in any one of at least first, second, third and fourth threshold voltage states, and where the first, second, third and fourth threshold voltage states correspond to four different data values defined by first and second bits. A page buffer circuit stores a logic value as main latch data and is responsive to a main latch signal to selectively flip the logic value of the main latch data according to a voltage level of the bit line. A sub-latch circuit stores a logic value as sub-latch data and is responsive to a sub-latch signal to selectively flip the logic value of the sub-latch data according to the voltage level of the bit line. The memory device is operable in a read mode which reads the threshold voltage state of the non-volatile memory cells and a programming mode which programs the threshold voltage state of the non-volatile memory cells, wherein the page buffer circuit is selectively responsive to the sub-latch data to inhibit flipping of the logic value of the main latch data in the programming mode.

Pattern inspection equipment has at least a measured data generation unit for generating measured data from patterns that have been delineated on a sample according to design data, a reference data generation unit for generating reference data used to inspect the patterns from gradational data expressed in multiple gradation levels, and a fault decision circuit for comparing the measured data with the reference data. The reference data generation unit has a multi-valued pattern development circuit for developing the design data into the gradational data and a fine adjustment circuit for finely shifting the positions or adjusting the curvatures of pattern edges in the pattern constructed with the gradational data. The fine adjustment of the pattern edges is necessary to cope with slightly displaced edges and rounded corners of the actual patterns on the sample. These slightly displaced edges and rounded corners are caused through mask manufacturing processes and are frequently smaller than the size of a sensor pixel. To adjust the reference data to the displaced edges, a size modification circuit detects a maximum value in a specified area in the gradational data and modifies the size of the pattern constructed with the gradational data. To adjust the reference data to match with the actual rounded corners, a corner rounding circuit rounds corners in the pattern constructed with the gradational data. Also provided is a pattern inspection method for developing the design data into the gradational data, adjusting the gradational data to displaced edges and rounded corners of the actual patterns and preparing the reference data, and testing the patterns for faults. Further provided is a storage medium for storing a pattern inspection program for realizing the pattern inspection method.

A programmable finite state machine (FSM) includes, in part, first and second memories, and a selection circuit coupled to each of the memories. Upon receiving a (k+m)-bit word representative of the k-bit input symbol and the m-bit current state, the first memory supplies one ore more matching transition rules stored therein. The selection circuit selects the most specific of the supplied rules. The transition rules are stored in the first memory in a ranking order of generality. The second memory receives the selected transition rule and supplies the next state of the FSM. The first memory may be a ternary content addressable memory and the second memory may be a static random access memory. The contents of both the content addressable memory and the static random memory is determined by an algorithm which minimizes the number of terms required to represent the next-state transition functions.