Semiconductor device and manufacturing method thereof

Abstract

There is formed a gate electrode (word line) via a gate insulating film on a semiconductor substrate, the gate electrode extending in the direction inclining at an angle of approximately 45 degrees to the extending direction of an element region. The element region is divided into three portions by the two gate electrodes. In each element region portion, two MOS transistors are provided. A bit line is connected to a W plug provided in the central region portion and lower electrodes of two ferroelectric capacitors are connected to other W plugs provided in both end region portions. The extending direction of the bit line inclines approximately 45 degrees to the extending direction of the element region.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS [0001] This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2003-364917, filed on Oct. 24, 2003, the entire contents of which are incorporated herein by reference. BACKGROUND OF THE INVENTION [0002] [Field of the Invention][0003] The present invention relates to a semiconductor device suitable for a ferroelectric memory and a manufacturing method thereof. [Description of the Related Art][0004] Recently, with the purpose of improving integration, the shape having a practically vertical side surface is expected for a shape of a ferroelectric capacitor for example of the 0.18 μm generation. For this purpose, for example in a simultaneous etching at a high temperature using a hard mask, such a technique is beginning to be employed as etching simultaneously an upper electrode film, a ferroelectric film, and a lower electrode film. As a structure of the hard mask here, a lamination structu...

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Benefits of technology

[0007] An object of the present invention is to provide a semiconductor device provided with a ferroelectric capacitor of a structure capable of reducing leakage current adequately while preventing local damages to a ferroelectric film, and a manufacturing method of the same.

[0010] Based on the above observational study, the present inventor has found that the adhering tendency of deposits to the sidewalls at the time of the high-temperature simultaneous etching depends not only on etching conditions but also on two factors in view of shape, namely the side length of the capacitor and the distance between the capacitors. From a different perspective, in the case of a layout of a conventional capacitor, as shown in FIG. 10 to FIG. 12, the distances between adjacent capacitors are different between those in the longitudinal direction and those in the lateral direction. This causes a difference between the amount of deposits on the longer sidewall and that on the shorter sidewall, making it difficult to adjust the etching conditions so as to reduce the leakage current while preventing the damages.

[0012] As shown in Table 1, a relation between the leakage current quotient L and the leakage current density of the capacitor is confirmed. The larger the former is, the higher the latter increases.

Problems solved by technology

On the other hand, at the shorter side of the capacitors, at which the distance between the capacitors are wider, deposits do not tend to adhere to the sidewalls, while there are damages on the capacitor insulating film.

This causes a difference between the amount of deposits on the longer sidewall and that on the shorter sidewall, making it difficult to adjust the etching conditions so as to reduce the leakage current while preventing the damages.

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