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59 results about "Clos network" patented technology

In the field of telecommunications, a Clos network is a kind of multistage circuit-switching network which represents a theoretical idealization of practical, multistage switching systems. It was invented by Edson Erwin in 1938 and first formalized by Charles Clos ([ʃaʁl klo])in 1952.

Nonblocking and deterministic multirate multicast packet scheduling

A system for scheduling multirate multicast packets through an interconnection network having a plurality of input ports, a plurality of output ports, and a plurality of input queues, comprising multirate multicast packets with rate weight, at each input port is operated in nonblocking manner in accordance with the invention by scheduling corresponding to the packet rate weight, at most as many packets equal to the number of input queues from each input port to each output port. The scheduling is performed so that each multicast packet is fan-out split through not more than two interconnection networks and not more than two switching times. The system is operated at 100% throughput, work conserving, fair, and yet deterministically thereby never congesting the output ports. The system performs arbitration in only one iteration, with mathematical minimum speedup in the interconnection network. The system operates with absolutely no packet reordering issues, no internal buffering of packets in the interconnection network, and hence in a truly cut-through and distributed manner. In another embodiment each output port also comprises a plurality of output queues and each packet is transferred corresponding to the packet rate weight, to an output queue in the destined output port in deterministic manner and without the requirement of segmentation and reassembly of packets even when the packets are of variable size. In one embodiment the scheduling is performed in strictly nonblocking manner with a speedup of at least three in the interconnection network. In another embodiment the scheduling is performed in rearrangeably nonblocking manner with a speedup of at least two in the interconnection network. The system also offers end to end guaranteed bandwidth and latency for multirate multicast packets from input ports to output ports. In all the embodiments, the interconnection network may be a crossbar network, shared memory network, clos network, hypercube network, or any internally nonblocking interconnection network or network of networks.
Owner:TEAK TECH

Reducing or eliminating routing microloops in networks having a clos topology, such as data center clos networks employing the exterior border gateway protocol (EBGP) for example

The problem of routing micro-loops in networks having a CLOS topology, such as data center CLOS networks employing the exterior border gateway protocol (eBGP) for example, is solved by: (a) receiving, on an interface of one of the nodes, a datagram, the datagram including destination information; (b) determining a next hop and an egress interface using (1) an identifier of the interface on which the datagram was received, (2) the destination information of the received datagram, and (3) stored forwarding information such that a routing micro-loop is avoided without discarding the datagram; and (c) forwarding the datagram via the egress interface. For example, this problem may be solved by (a) receiving, on an interface a node of the CLOS network, a datagram, the datagram including destination information; (b) looking up, using the destination information of the received datagram and stored forwarding information, a next hop egress interface on the node; (c) determining whether or not the next hop egress interface on the node is the same as the interface on which the datagram was received; and (d) responsive to a determination that the next hop egress interface on the node is the same as the interface on which the datagram was received, (1) replacing the next hop egress interface with a safe multipath next hop egress interface, and (2) forwarding the datagram via the safe multipath next hop egress interface, and otherwise, responsive to a determination that the next hop egress interface on the node is not the same at the interface on which the datagram was received, simply forwarding the datagram via the next hop egress interface.
Owner:JUMIPER NETWORKS INC

Nonblocking and deterministic unicast packet scheduling

A system for scheduling unicast packets through an interconnection network having a plurality of input ports, a plurality of output ports, and a plurality of input queues, comprising unicast packets, at each input port is operated in nonblocking manner in accordance with the invention by scheduling at most as many packets equal to the number of input queues from each input port to each output port. The system is operated at 100% throughput, work conserving, fair, and yet deterministically thereby never congesting the output ports. The system performs arbitration in only one iteration, with mathematical minimum speedup in the interconnection network. The system operates with absolutely no packet reordering issues, no internal buffering of packets in the interconnection network, and hence in a truly cut-through and distributed manner. In another embodiment each output port also comprises a plurality of output queues and each packet is transferred to an output queue in the destined output port in nonblocking and deterministic manner and without the requirement of segmentation and reassembly of packets even when the packets are of variable size. In one embodiment the scheduling is performed in strictly nonblocking manner with a speedup of at least two in the interconnection network. In another embodiment the scheduling is performed in rearrangeably nonblocking manner with a speedup of at least one in the interconnection network. The system also offers end to end guaranteed bandwidth and latency for packets from input ports to output ports. In all the embodiments, the interconnection network may be a crossbar network, shared memory network, clos network, hypercube network, or any internally nonblocking interconnection network or network of networks.
Owner:TEAK TECH

Nonblocking and deterministic multicast packet scheduling

A system for scheduling multicast packets through an interconnection network having a plurality of input ports, a plurality of output ports, and a plurality of input queues, comprising multicast packets, at each input port is operated in nonblocking manner in accordance with the invention by scheduling at most as many packets equal to the number of input queues from each input port to each output port. The scheduling is performed so that each multicast packet is fan-out split through not more than two interconnection networks and not more than two switching times. The system is operated at 100% throughput, work conserving, fair, and yet deterministically thereby never congesting the output ports. The system performs arbitration in only one iteration, with mathematical minimum speedup in the interconnection network. The system operates with absolutely no packet reordering issues, no internal buffering of packets in the interconnection network, and hence in a truly cut-through and distributed manner. In another embodiment each output port also comprises a plurality of output queues and each packet is transferred to an output queue in the destined output port in nonblocking and deterministic manner and without the requirement of segmentation and reassembly of packets even when the packets are of variable size. In one embodiment the scheduling is performed in strictly nonblocking manner with a speedup of at least three in the interconnection network. In another embodiment the scheduling is performed in rearrangeably nonblocking manner with a speedup of at least two in the interconnection network. The system also offers end to end guaranteed bandwidth and latency for multicast packets from input ports to output ports. In all the embodiments, the interconnection network may be a crossbar network, shared memory network, clos network, hypercube network, or any internally nonblocking interconnection network or network of networks.
Owner:TEAK TECH

Orderly packet routing and scheduling method in clos network

ActiveCN104486237ASolve group disorderSolve the problem of not being able to exchange at high speedData switching networksIntermediate stageDistributed computing
The invention discloses an orderly packet routing and scheduling method in a Clos network, and mainly aims to solve the problem that pockets cannot be exchanged at high speed and are exchanged with disorders in the prior art. The technical scheme adopted by the invention is that the orderly packet routing and scheduling method comprises the following steps: 1, a first-stage virtual output queue group is used for sending a request to a first-stage output port, and the output port is used for selecting a request approval with a maximum weight; 2, the first-stage virtual output queue group is selected to be matched with one output port; 3, the first-stage virtual output queue group is used for selecting a virtual output queue in an input port to be matched with the output port; 4, a first-stage matched output port is used for sending a request to an intermediate stage; 5, a first stage is used for sending packets to a third-stage input cache by passing through the intermediate stage after the intermediate stage responds; 6, the third-stage input cache is used for sending the packets to a cross node cache; 7, the pockets are taken out of the cross node cache and are output. The orderly packet routing and scheduling method is capable of ensuring that the packets are exchanged at high speed and are orderly exchanged; the high throughput can be realized; the orderly packet routing and scheduling method is suitable for high-speed and large-capacity exchangers and routers.
Owner:XIDIAN UNIV

Nonblocking and deterministic multirate unicast packet scheduling

A system for scheduling multirate unicast packets through an interconnection network having a plurality of input ports, a plurality of output ports, and a plurality of input queues, comprising multirate unicast packets with rate weight, at each input port is operated in nonblocking manner in accordance with the invention by scheduling corresponding to the packet rate weight, at most as many packets equal to the number of input queues from each input port to each output port. The system is operated at 100% throughput, work conserving, fair, and yet deterministically thereby never congesting the output ports. The system performs arbitration in only one iteration, with mathematical minimum speedup in the interconnection network. The system operates with absolutely no packet reordering issues, no internal buffering of packets in the interconnection network, and hence in a truly cut-through and distributed manner. In another embodiment each output port also comprises a plurality of output queues and each packet is transferred corresponding to the packet rate weight, to an output queue in the destined output port in deterministic manner and without the requirement of segmentation and reassembly of packets even when the packets are of variable size. In one embodiment the scheduling is performed in strictly nonblocking manner with a speedup of at least two in the interconnection network. In another embodiment the scheduling is performed in rearrangeably nonblocking manner with a speedup of at least one in the interconnection network. The system also offers end to end guaranteed bandwidth and latency for multirate packets from input ports to output ports. In all the embodiments, the interconnection network may be a crossbar network, shared memory network, clos network, hypercube network, or any internally nonblocking interconnection network or network of networks.
Owner:TEAK TECH

Improved three-level CLOS routing algorithm based on FPGA crossover

ActiveCN109327410ALarge Routing Cross CapabilityMeeting large-capacity crossover requirementsMultiplex system selection arrangementsData switching networksThree levelIntermediate level
The invention relates to an improved three-level CLOS routing algorithm based on FPGA crossover. Based on the internal crossover capability of the FPGA, the invention realizes a routing nesting algorithm of the two-layer three-level CLOS network for realizing the input and output routing crossover function of an optical fiber signal. The first layer of three-level CLOS network increases a design strategy of intermediate-level merge, and the connection between the input and output stages and the switching stage is increased from one connection channel of the traditional architecture to four connection channels, which increases the routing space. The second layer of CLOS network calculates the on-chip routing of the FPGA, and implements a direct-cut mode in the scenario of board crossover without occupying the switching-level resources to increase the routing space, thereby having the advantage of greatly reducing the blocking rate in the scenario of large-capacity crossover. The improved three-level CLOS routing algorithm based on FPGA crossover increases the routing space through the improvement of the architecture and the algorithm, greatly reduces the blocking rate, and improvesthe equipment performance advantage and user experience.
Owner:TOEC TECH

FEC decoding system with optical line crossing function realized based on electric domain and method

InactiveCN106487483AImplement cross-functionalityRealize the function of solving FECError preventionDistortion/dispersion eliminationThree levelLevel crossing
The invention relates to an FEC decoding system with an optical line crossing function realized based on an electric domain and a method. The system adopts a structure in which cards are plugged into a backboard. The plug-in cards comprise an interface board, an FEC decoding board, a first-level cross board, a second-level cross board, and a master control board. The system is based on a three-level rigorous obstruction-free CLOS network. Input-level crossing and output-level crossing are completed by high-speed cross chips distributed on the cross boards. Intermediate-level crossing is completed by an FPGA on the FEC decoding board. Three kinds of board cards form a rigorous obstruction-free cross network. The FPGA chip on the FEC decoding board also completes an FEC decoding function. The interface board is responsible for accessing and outputting optical signals and achieving an O / E / O function. The master control board is responsible for receiving an instruction from a principal computer and communicating with other board cards. With the system, the function of FEC decoding at multiple rates can be achieved, and optical channels can be crossed by means of O / E / O. Moreover, the system has broadcast and replication functions.
Owner:TOEC TECH
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