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Improved three-level CLOS routing algorithm based on FPGA crossover

A routing and algorithm technology, applied in the field of improved three-level CLOS routing algorithm based on FPGA cross, can solve the problems of cross switching capability and blocking that cannot meet the large capacity, meet the needs of large capacity cross, increase flexibility, solve large The effect of capacity crossing on demand

Active Publication Date: 2019-02-12
TOEC TECH
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  • Summary
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AI Technical Summary

Benefits of technology

In this patented technology, there has been developed an efficient way to connect multiple electronic components together through various techniques such as interfacing between different types of networks (FPN) or connecting them via connections called jumpers. By combining these technologies into a larger capacity system, it becomes possible to handle more data faster than previous methods like synchronous digital hierarchy). Overall, this technology enhances how we communicate over long distances while reducing costs associated with building up powerful computer systems.

Problems solved by technology

This patented technical problem addressed by this patents relates to improving the performance of Optically Switched Networks (OCN), specifically their ability to efficiently transmit high volumes of digital signals over long distances without causing delays or errors during signal processing due to blocked paths caused by specific types of connections between different layers within these networks.

Method used

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  • Improved three-level CLOS routing algorithm based on FPGA crossover
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  • Improved three-level CLOS routing algorithm based on FPGA crossover

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Embodiment Construction

[0025] The operating platform of the present invention is a large-capacity TBits-level crossover device. The device needs to be filled with 12 service boards, 2 switching boards, and 1 main control board. After the device is powered on, the control program on each board starts, and each board The running status light of the upper board card shows that the device control network management and the device are interconnected through a network cable or a switch, so that the two can communicate in the same LAN. Address, port number, device id, etc., enter the control interface of the TBits-level device, check the status of the board, click the business view, in the business view, you can perform operations such as creating a new cross-connect / deleting a cross-connect, and clicking the new cross-connect will pop up a cross-connect information input box. Select the input and output board number / input and output port number / output signal type / output granularity / output bandwidth. If the...

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Abstract

The invention relates to an improved three-level CLOS routing algorithm based on FPGA crossover. Based on the internal crossover capability of the FPGA, the invention realizes a routing nesting algorithm of the two-layer three-level CLOS network for realizing the input and output routing crossover function of an optical fiber signal. The first layer of three-level CLOS network increases a design strategy of intermediate-level merge, and the connection between the input and output stages and the switching stage is increased from one connection channel of the traditional architecture to four connection channels, which increases the routing space. The second layer of CLOS network calculates the on-chip routing of the FPGA, and implements a direct-cut mode in the scenario of board crossover without occupying the switching-level resources to increase the routing space, thereby having the advantage of greatly reducing the blocking rate in the scenario of large-capacity crossover. The improved three-level CLOS routing algorithm based on FPGA crossover increases the routing space through the improvement of the architecture and the algorithm, greatly reduces the blocking rate, and improvesthe equipment performance advantage and user experience.

Description

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Claims

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Application Information

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Owner TOEC TECH
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